Ch1_Wr_Sec (CPM4_DMA_ATTR) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

Ch1_Wr_Sec (CPM4_DMA_ATTR) Register Description

Register NameCh1_Wr_Sec
Relative Address0x00000008D0
Absolute Address 0x00FCA708D0 (CPM4_DMA_ATTR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionARPROT value used for DMA AXIMM writes from channel1

This register should only be written to during reset of the PCIe block Alternate register name: attr_dma_ch1_wr_sec

Ch1_Wr_Sec (CPM4_DMA_ATTR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr 0rwNormal read/write0x0ARPROT value used for DMA AXIMM writes from channel1