Ch2_MultQ (CPM4_DMA_ATTR) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

Ch2_MultQ (CPM4_DMA_ATTR) Register Description

Register NameCh2_MultQ
Relative Address0x0000000914
Absolute Address 0x00FCA70914 (CPM4_DMA_ATTR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionThe channel has multiq enabled.
1 - MULTQ,
0 - XDMA

This register should only be written to during reset of the PCIe block Alternate register name: attr_dma_ch2_multq

Ch2_MultQ (CPM4_DMA_ATTR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr 0rwNormal read/write0x0The channel has multiq enabled.
1 - MULTQ,
0 - XDMA