Ch2_Rd_Cache (CPM4_DMA_ATTR) Register Description
Register Name | Ch2_Rd_Cache |
Relative Address | 0x0000000900 |
Absolute Address |
0x00FCA70900 (CPM4_DMA_ATTR)
|
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | ARCACHE value used for DMA AXIMM reads from channel2 |
This register should only be written to during reset of the PCIe block Alternate register name: attr_dma_ch2_rd_cache
Ch2_Rd_Cache (CPM4_DMA_ATTR) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
attr | 3:0 | rwNormal read/write | 0x0 | ARCACHE value used for DMA AXIMM reads from channel2 |