Ch3_Wr_Cache (CPM4_DMA_ATTR) Register Description
| Register Name | Ch3_Wr_Cache |
|---|
| Relative Address | 0x0000000930 |
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| Absolute Address |
0x00FCA70930 (CPM4_DMA_ATTR)
|
|---|
| Width | 32 |
|---|
| Type | rwNormal read/write |
|---|
| Reset Value | 0x00000000 |
|---|
| Description | ARCACHE value used for DMA AXIMM writes from channel3 |
|---|
This register should only be written to during reset of the PCIe block Alternate register name: attr_dma_ch3_wr_cache
Ch3_Wr_Cache (CPM4_DMA_ATTR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|
| attr | 3:0 | rwNormal read/write | 0x0 | ARCACHE value used for DMA AXIMM writes from channel3 |