DataPhase_BaudRate (CANFD) Register Description
Register Name | DataPhase_BaudRate |
---|---|
Relative Address | 0x0000000088 |
Absolute Address |
0x00FF060088 (CANFD0) 0x00FF070088 (CANFD1) |
Width | 17 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | Data Phase Baud Rate Prescaler |
The following boundary conditions are imposed on sum of measured loop delay and TDC Offset: Measured loop delay + TDCOFF < 3 bit times in the data phase Ensure that the boundary condition is respected while programming Offset and data phase bit rate. In case this sum exceeds 127 CAN clock periods, the maximum value of 127 CAN clock periods is used by core for transmitter delay compensation. NOTE: If loop delay is < 1 data phase bit time, then TDC/SSP method is not needed. Software Driver name: XCANFD_F_BRPR Alternate register name: Data_Phase_Baud_Rate_Prescaler_Register
DataPhase_BaudRate (CANFD) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
TDC | 16 | rwNormal read/write | 0x0 | Transmitter Delay Compensation (TDC) Enable 1 = enables TDC function as specified in the CAN FD standard 0 = TDC is disabled This bit can be written only when CEN bit in SRR is 0. |
TDCOFF | 13:8 | rwNormal read/write | 0x0 | Transmitter Delay Compensation Offset This offset is specified in CAN clock cycles and is added to the measured transmitter delay to place the Secondary Sample Point (SSP) at appropriate position (for example, set this to half data bit time in terms of CAN clock cycles to place SSP in the middle of the data bit). This bit can be written only when CEN bit in SRR is 0. |
DP | 7:0 | rwNormal read/write | 0x0 | Data Phase Baud Rate Prescaler These bits indicate the prescaler value for Data Bit Timing as specified in the CAN FD standard. The actual value is one more than the value written to the register. This bit can be written only when CEN bit in SRR is 0. Note: Field name reference: DP_BRP |