DataPhase_BitTiming (CANFD) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

DataPhase_BitTiming (CANFD) Register Description

Register NameDataPhase_BitTiming
Relative Address0x000000008C
Absolute Address 0x00FF06008C (CANFD0)
0x00FF07008C (CANFD1)
Width20
TyperwNormal read/write
Reset Value0x00000000
DescriptionData Phase Bit Timing

Software Driver name: XCANFD_F_BTR Alternate register name: Data_Phase_Bit_Timing_Register

DataPhase_BitTiming (CANFD) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
DP_SJW19:16rwNormal read/write0x0Data Phase Synchronization Jump Width
Indicates the Synchronization Jump Width as specified in the CAN FD standard for Data Bit Timing.
The actual value is one more than the value written to the register.
This bit can be written only when CEN bit in SRR is 0.
DP_TS211:8rwNormal read/write0x0Data Phase Time Segment 2
Indicates the Phase Segment 2 as specified in the CAN FD standard for Data Bit Timing.
The actual value is one more than the value written to the register.
This bit can be written only when CEN bit in SRR is 0.
DP_TS1 4:0rwNormal read/write0x0Data Phase Time Segment 1
Indicates the Sum of Propagation Segment and Phase Segment 1 as specified in the CAN FD standard for Data Bit Timing.
The actual value is one more than the value written to the register.
This bit can be written only when CEN bit in SRR is 0.