Error_Count (CANFD) Register Description
| Register Name | Error_Count |
|---|---|
| Relative Address | 0x0000000010 |
| Absolute Address |
0x00FF060010 (CANFD0) 0x00FF070010 (CANFD1) |
| Width | 16 |
| Type | roRead-only |
| Reset Value | 0x00000000 |
| Description | Error Count |
The value of the error counters in the register reflect the values of the transmit and receive error counters in the core. The following conditions reset the Transmit and Receive Error counters: * When 1 is written to the SW_Reset [SRST] bit. * When 0 is written to the SW_Reset [CEN] bit. * When core enters Bus-Off state. * During Bus-Off recovery until the core enters Error Active state (after 128 occurrences of 11 consecutive recessive bits). Note: When in Bus-Off recovery, the Receive Error counter is advanced/incremented by 1 when a sequence of 11 consecutive nominal recessive bits is seen. Note: In SNOOP mode, error counters are disabled and cleared to 0. Reads to Error_Count register returns 0. Note: The Error_Count is a read-only register. Writes to the ECR have no effect. Software Driver name: XCANFD_ECR Alternate register name: Error_Counter_Register
Error_Count (CANFD) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| REC | 15:8 | roRead-only | 0x0 | Receive Error Count Indicates the value of Receive Error Counter. |
| TEC | 7:0 | roRead-only | 0x0 | Transmit Error Count Indicates the value of Transmit Error Counter. |