Error_Status (CANFD) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

Error_Status (CANFD) Register Description

Register NameError_Status
Relative Address0x0000000014
Absolute Address 0x00FF060014 (CANFD0)
0x00FF070014 (CANFD1)
Width12
TypewtcReadable, write a 1 to clear
Reset Value0x00000000
DescriptionError Status

The error status register indicates the type of error that has occurred on the CAN bus. If more than one error occurs, all relevant error flag bits are set = 1. The error bits are sticky, they remain set until cleared by writing a 1 to the bit. Read: 0: no error 1: error or errors detected Write: 0: no effect 1: clears bit to 0 Note 1: In transmitter delay compensation phase, any error is reported as fast bit error (by the transmitter). Note 2: Fixed stuff bit errors are reported as form error, [FMER]. Note 3: In case of a CRC Error and a CRC delimiter corruption, only the [FMER] bit is set. Software Driver name: XCANFD_ESR Alternate register name: Error_Status_Register

Error_Status (CANFD) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
F_BERR11wtcReadable, write a 1 to clear0x0Bit Error in CAN FD Data Phase
1 = indicates bit error occurred in Data Phase (Fast) data rate
0 = indicates bit error has not occurred in Data Phase (Fast) data rate after the last write to this bit
If this bit is set, writing a 1 clears it.
F_STER10wtcReadable, write a 1 to clear0x0Stuff Error in Data Phase indicator:
0: error has not occurred in Data Phase (Fast) data rate after the last write to this bit.
1: error occurred in Data Phase (Fast) data rate
Note: Write a 1 to clear this bit.
F_FMER 9wtcReadable, write a 1 to clear0x0Form Error Indicator in Data Phase:
0: error has not occurred in Data Phase (Fast) data rate after the last write to this bit.
1: error occurred in Data Phase (Fast) data rate
Note: Write a 1 to clear this bit.
F_CRCER 8wtcReadable, write a 1 to clear0x0CRC Error in CAN FD Data Phase
1 = indicates CRC error occurred in Data Phase (Fast) data rate
0 = indicates CRC error has not occurred in Data Phase (Fast) data rate after the last write to this bit.
If this bit is set, writing a 1 clears it.
ACKER 4wtcReadable, write a 1 to clear0x0ACK Error
Indicates an acknowledgement error.
1 = indicates an acknowledgement error has occurred
0 = indicates an acknowledgement error has not occurred on the bus after the last write to this bit
If this bit is set, writing a 1 clears it.
BERR 3wtcReadable, write a 1 to clear0x0Bit Error. Indicates the received bit is not the same as the transmitted bit during bus communication.
1 = indicates a bit error has occurred
0 = indicates a bit error has not occurred on the bus after the last write to this bit
If this bit is set, writing a 1 clears it.
STER 2wtcReadable, write a 1 to clear0x0Stuff Error. Indicates an error if there is a stuffing violation.
1 = indicates a stuff error has occurred
0 = indicates a stuff error has not occurred on the bus after the last write to this bit
If this bit is set, writing a 1 clears it.
FMER 1wtcReadable, write a 1 to clear0x0Form Error. Indicates an error in one of the fixed form fields in the message frame.
1 = indicates a form error has occurred
0 = indicates a form error has not occurred on the bus after the last write to this bit
If this bit is set, writing a 1 clears it.
CRCER 0wtcReadable, write a 1 to clear0x0CRC Error. Indicates a CRC error has occurred.
1 = indicates a CRC error has occurred
0 = indicates a CRC error has not occurred on the bus after the last write to this bit
If this bit is set, writing a 1 clears it.