GICD_SGIR (APU_GIC_DIST_MAIN) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

GICD_SGIR (APU_GIC_DIST_MAIN) Register Description

Register NameGICD_SGIR
Relative Address0x0000000F00
Absolute Address 0x00F9000F00 (APU_GIC_DIST_MAIN)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionSoftware Generated Interrupt Register

GICD_SGIR (APU_GIC_DIST_MAIN) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
GICD_SGIR_25_2425:24rwNormal read/write0Software Generated Interrupt Register
GICD_SGIR_23_1623:16rwNormal read/write0Software Generated Interrupt Register
GICD_SGIR_1515rwNormal read/write0Software Generated Interrupt Register
GICD_SGIR_3_0 3:0rwNormal read/write0Software Generated Interrupt Register