GICH_LR0 (APU_GIC_A72_VIFCTL) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

GICH_LR0 (APU_GIC_A72_VIFCTL) Register Description

Register NameGICH_LR0
Relative Address0x0000000100
Absolute Address 0x00F9050100 (APU_GIC_VIFCTL)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionGICH_LR0

GICH_LR0 (APU_GIC_A72_VIFCTL) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
HW31rwNormal read/write0
Grp130rwNormal read/write0
State29:28rwNormal read/write0
Priority27:23rwNormal read/write0
PhysicalID19:10rwNormal read/write0
VirtualID 9:0rwNormal read/write0