GICH_LR0 (APU_GIC_A72_VIFCTL) Register Description
Register Name | GICH_LR0 |
---|---|
Relative Address | 0x0000000100 |
Absolute Address | 0x00F9050100 (APU_GIC_VIFCTL) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | GICH_LR0 |
GICH_LR0 (APU_GIC_A72_VIFCTL) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
HW | 31 | rwNormal read/write | 0 | |
Grp1 | 30 | rwNormal read/write | 0 | |
State | 29:28 | rwNormal read/write | 0 | |
Priority | 27:23 | rwNormal read/write | 0 | |
PhysicalID | 19:10 | rwNormal read/write | 0 | |
VirtualID | 9:0 | rwNormal read/write | 0 |