GICR_ISENABLER0 (APU_GIC_REDIST_SGISPI) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

GICR_ISENABLER0 (APU_GIC_REDIST_SGISPI) Register Description

Register NameGICR_ISENABLER0
Relative Address0x0000000100
Absolute Address 0x00F9090100 (APU_GIC_REDIST_SGISPI_0)
0x00F90B0100 (APU_GIC_REDIST_SGISPI_1)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionInterrupt Set-Enable Registers

GICR_ISENABLER0 (APU_GIC_REDIST_SGISPI) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
_31:0rwNormal read/write0x0Interrupt Set-Enable Registers