GICR_PENDBASER_upper (APU_GIC_REDIST_CTLLPI) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

GICR_PENDBASER_upper (APU_GIC_REDIST_CTLLPI) Register Description

Register NameGICR_PENDBASER_upper
Relative Address0x000000007C
Absolute Address 0x00F908007C (APU_GIC_REDIST_CTLLPI_0)
0x00F90A007C (APU_GIC_REDIST_CTLLPI_1)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionLPI Pending Table Control Register (upper)

GICR_PENDBASER_upper (APU_GIC_REDIST_CTLLPI) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
GICR_PENDBASER_upper_3030rwNormal read/write0x0LPI Pending Table Control Register (upper)
GICR_PENDBASER_upper_15_015:0rwNormal read/write0x0LPI Pending Table Control Register (upper)