GITS_BASER0_lower (APU_GIC_ITS_CTL) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

GITS_BASER0_lower (APU_GIC_ITS_CTL) Register Description

Register NameGITS_BASER0_lower
Relative Address0x0000000100
Absolute Address 0x00F9020100 (APU_GIC_ITS_CTL)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionITS Table Control Register (lower)

GITS_BASER0_lower (APU_GIC_ITS_CTL) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
GITS_BASER0_lower_31_1231:12rwNormal read/write0x0ITS Table Control Register (lower)
GITS_BASER0_lower_9_8 9:8rwNormal read/write0x0ITS Table Control Register (lower)
GITS_BASER0_lower_7_0 7:0rwNormal read/write0x0ITS Table Control Register (lower)