GITS_CBASER_upper (APU_GIC_ITS_CTL) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

GITS_CBASER_upper (APU_GIC_ITS_CTL) Register Description

Register NameGITS_CBASER_upper
Relative Address0x0000000084
Absolute Address 0x00F9020084 (APU_GIC_ITS_CTL)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionCommand Queue Control Register (upper)

GITS_CBASER_upper (APU_GIC_ITS_CTL) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
GITS_CBASER_upper_3131rwNormal read/write0x0Note: changing bits 15:12 makes no effect, since only 44 address bits are supported
GITS_CBASER_upper_29_2729:27rwNormal read/write0x0Note: changing bits 15:12 makes no effect, since only 44 address bits are supported
GITS_CBASER_upper_15_015:0rwNormal read/write0x0Note: changing bits 15:12 makes no effect, since only 44 address bits are supported