IDR (CPM4_DMA_ATTR) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

IDR (CPM4_DMA_ATTR) Register Description

Register NameIDR
Relative Address0x000000001C
Absolute Address 0x00FCA7001C (CPM4_DMA_ATTR)
Width32
TypewoWrite-only
Reset Value0x00000000
DescriptionAPB Interrupt Disable

Disable Interrupt Bits (write-only): 0: no effect 1: sets the mask bit = 1 (disables the interrupt signal) Note: Refer to the ISR register for more information.

IDR (CPM4_DMA_ATTR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
addr_decode_err 0woWrite-only0x0Address Decode Error