Field Name | Bits | Type | Reset Value | Description |
Reserved | 31:7 | roRead-only | 0x0 | Reserved |
araddr_mismatch2 | 6 | wtcReadable, write a 1 to clear | 0x0 | Read address mismatch on Port 2 |
araddr_mismatch1 | 5 | wtcReadable, write a 1 to clear | 0x0 | Read address mismatch on Port 1 |
araddr_mismatch0 | 4 | wtcReadable, write a 1 to clear | 0x0 | Read address mismatch on Port 0 |
awaddr_mismatch2 | 3 | wtcReadable, write a 1 to clear | 0x0 | Write address mismatch on Port 2 |
awaddr_mismatch1 | 2 | wtcReadable, write a 1 to clear | 0x0 | Write address mismatch on Port 1 |
awaddr_mismatch0 | 1 | wtcReadable, write a 1 to clear | 0x0 | Write address mismatch on Port 0 |
addr_decode_err | 0 | wtcReadable, write a 1 to clear | 0x0 | Address decode error in this register block |