MISC_CTRL (CPM4_DMA_ATTR) Register Description
| Register Name | MISC_CTRL |
|---|---|
| Relative Address | 0x0000000000 |
| Absolute Address | 0x00FCA70000 (CPM4_DMA_ATTR) |
| Width | 1 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | MISC_CTRL |
MISC_CTRL (CPM4_DMA_ATTR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| enable | 0 | rwNormal read/write | 0x0 | Enable the APB error signal to assert when an error is detected during an access to the register module. 0: disable error signaling (APB_Err is kept low) 1: assert the APB_Err signal when a register access error is detected Note: When an APB error occurs, the interrupt status bit in the ISR will be set regardless of this enable bit setting. Note: Field name reference: slverr_enable |