Module Name | Module Type | Base Address | Description |
---|
APU_DUAL_CSR | APU_DUAL_CSR | 0x00FD5C0000 | APU MPCore Dual Processor Control (aka APU_DUAL) |
APU_GIC_CPUIF | APU_GIC_A72_CPUIF | 0x00F9040000 | APU GIC CPU Interface |
APU_GIC_DIST_MAIN | APU_GIC_DIST_MAIN | 0x00F9000000 | APU GIC Main Distribution |
APU_GIC_DIST_MBSPI | APU_GIC_DIST_MBSPI | 0x00F9010000 | APU GIC Distributor for Message-based SPIs |
APU_GIC_ITS_CTL | APU_GIC_ITS_CTL | 0x00F9020000 | APU GIC Interrupt Translation Service Control |
APU_GIC_ITS_TRANS | APU_GIC_ITS_TRANS | 0x00F9030000 | APU GIC Interrupt Translation Service |
APU_GIC_REDIST_CTLLPI_0 | APU_GIC_REDIST_CTLLPI | 0x00F9080000 | APU GIC Redistribution Control, CPU 0 |
APU_GIC_REDIST_CTLLPI_1 | APU_GIC_REDIST_CTLLPI | 0x00F90A0000 | APU GIC Redistribution Control, CPU 1 |
APU_GIC_REDIST_SGISPI_0 | APU_GIC_REDIST_SGISPI | 0x00F9090000 | APU GIC Redistribution Interrupts, CPU 0 |
APU_GIC_REDIST_SGISPI_1 | APU_GIC_REDIST_SGISPI | 0x00F90B0000 | APU GIC Redistribution Interrupts, CPU 1 |
APU_GIC_VCPUIF | APU_GIC_A72_VCPUIF | 0x00F9060000 | APU GIC Virtual CPU Interface |
APU_GIC_VIFCTL | APU_GIC_A72_VIFCTL | 0x00F9050000 | APU GIC Virtual Interface Control |
CANFD0 | CANFD | 0x00FF060000 | CAN FD Controller, Controller 0 |
CANFD1 | CANFD | 0x00FF070000 | CAN FD Controller, Controller 1 |
CFRAME00_REG | CFRAME_REG | 0x00F12D0000 | CFRAME Configuration, Frame 00 |
CFRAME01_REG | CFRAME_REG | 0x00F12D2000 | CFRAME Configuration, Frame 01 |
CFRAME02_REG | CFRAME_REG | 0x00F12D4000 | CFRAME Configuration, Frame 02 |
CFRAME03_REG | CFRAME_REG | 0x00F12D6000 | CFRAME Configuration, Frame 03 |
CFRAME04_REG | CFRAME_REG | 0x00F12D8000 | CFRAME Configuration, Frame 04 |
CFRAME05_REG | CFRAME_REG | 0x00F12DA000 | CFRAME Configuration, Frame 05 |
CFRAME06_REG | CFRAME_REG | 0x00F12DC000 | CFRAME Configuration, Frame 06 |
CFRAME07_REG | CFRAME_REG | 0x00F12DE000 | CFRAME Configuration, Frame 07 |
CFRAME08_REG | CFRAME_REG | 0x00F12E0000 | CFRAME Configuration, Frame 08 |
CFRAME09_REG | CFRAME_REG | 0x00F12E2000 | CFRAME Configuration, Frame 09 |
CFRAME10_REG | CFRAME_REG | 0x00F12E4000 | CFRAME Configuration, Frame 10 |
CFRAME11_REG | CFRAME_REG | 0x00F12E6000 | CFRAME Configuration, Frame 11 |
CFRAME12_REG | CFRAME_REG | 0x00F12E8000 | CFRAME Configuration, Frame 12 |
CFRAME13_REG | CFRAME_REG | 0x00F12EA000 | CFRAME Configuration, Frame 13 |
CFRAME14_REG | CFRAME_REG | 0x00F12EC000 | CFRAME Configuration, Frame 14 |
CFRAME_BCAST_REG | CFRAME_REG | 0x00F12EE000 | CFRAME Configuration, Frame 15 - Broadcast |
CFU_CSR | CFU_CSR | 0x00F12B0000 | CFU Configuration Unit (aka CFU_APB) |
CPM4_ADDRREMAP | CPM4_ADDRREMAP | 0x00FCF30000 | CPM4 Address ReMap |
CPM4_CMN | CPM4_CMN600 | 0x00FC000000 | CPM4 CMN Registers |
CPM4_CRX | CPM4_CRX | 0x00FCA00000 | CPM4 Clock and Resets Controllers (aka CPM_CRCPM) |
CPM4_DMA_ATTR | CPM4_DMA_ATTR | 0x00FCA70000 | CPM4 PCIe DMA Attributes |
CPM4_DVSEC0 | CPM4_DVSEC0 | 0x00FCFB0000 | CPM4 PCIe Controller 0 Device Security |
CPM4_DVSEC1 | CPM4_DVSEC1 | 0x00FCFC0000 | CPM4 PCIe Controller 1 Device Security |
CPM4_INT_CSR | CPM4_INT_CSR | 0x00FCB40000 | CPM4 Interconnect (aka INTCPM_CONFIG) |
CPM4_INT_GPV | CPM4_INT_GPV | 0x00FCB00000 | CPM4 Interconnect GPV (aka CPM_INT_GPV) |
CPM4_L2_CSR | CPM4_L2_CSR | 0x00FCD00000 | CPM4 L2 Cache Registers (aka CPM_L2_REGS) |
CPM4_PCIE0_ATTR | CPM4_PCIE0_ATTR | 0x00FCA50000 | CPM4 PCIe0 Attributes (program with design tools) |
CPM4_PCIE1_ATTR | CPM4_PCIE1_ATTR | 0x00FCA60000 | CPM4 PCIe1 Attributes (program with design tools) |
CPM4_SLCR | CPM4_SLCR | 0x00FCA10000 | CPM4 SLCR Registers |
CPM4_SLCR_SECURE | CPM4_SLCR_SECURE | 0x00FCA20000 | CPM4 SLCR Secure Registers |
CPM4_XDMA_CSR | CPM4_XDMA_CSR | 0x00E1000000 | CPM4 DMA Registers (aka XDMA_REG) |
CPM5_ADDRREMAP | CPM5_ADDRREMAP | 0x00FCDB0000 | CPM5 Address ReMap, CPM5 Address Remap Control |
CPM5_CMN | CPM5_CMN600 | 0x00FC000000 | CPM5 CMN Registers, CPM5 Cache Mesh Network |
CPM5_CRX | CPM5_CRX | 0x00FCDC0000 | CPM5 Clock and Resets, CPM5 Clock and Reset Registers |
CPM5_DMA0_ATTR | CPM5_DMA_ATTR | 0x00FCE10000 | CPM5 DMA Attributes, CPM5 DMA Controller 0 Attributes |
CPM5_DMA0_CSR | CPM5_DMA_CSR | 0x00FCE20000 | CPM5 DMA Bridge, CPM5 DMA Controller 0 Control and Status |
CPM5_DMA1_ATTR | CPM5_DMA_ATTR | 0x00FCE90000 | CPM5 DMA Attributes, CPM5 DMA Controller 1 Attributes |
CPM5_DMA1_CSR | CPM5_DMA_CSR | 0x00FCEA0000 | CPM5 DMA Bridge, CPM5 DMA Controller 1 Control and Status |
CPM5_DVSEC0 | CPM5_DVSEC | 0x00FCE40000 | CPM5 Device Security (aka PCIEA5_DVSEC), CPM5 Device Security Controller 0 |
CPM5_DVSEC1 | CPM5_DVSEC | 0x00FCEC0000 | CPM5 Device Security (aka PCIEA5_DVSEC), CPM5 Device Security Controller 1 |
CPM5_INT_CSR | CPM5_INT_CSR | 0x00FCA00000 | CPM5 Interconnect (aka INTCPM5_CONFIG), CPM5 Interconnect Configuration |
CPM5_INT_GPV | CPM5_INT_GPV | 0x00FCD80000 | CPM5 Interconnect GPV, CPM5 Global View Interconnect Control |
CPM5_L20_CSR | CPM5_L2_CFG | 0x00FCC00000 | CPM5 L2 Cache Registers (aka CPM_L2_REGS), CPM5 L2 Cache 0 Control and Status |
CPM5_L21_CSR | CPM5_L2_CFG | 0x00FCC80000 | CPM5 L2 Cache Registers (aka CPM_L2_REGS), CPM5 L2 Cache 1 Control and Status |
CPM5_PCIE0_ATTR | CPM5_PCIE_ATTR | 0x00FCE08000 | CPM5 PCIe Attributes (program with design tools) (aka PCIEA5_ATTRIB), CPM5 PCIe Controller 0 Attributes |
CPM5_PCIE0_CSR | CPM5_PCIE_CSR | 0x00FCE00000 | CPM5 PCIe Control and Status, CPM5 PCIe Controller 0 Control and Status |
CPM5_PCIE1_ATTR | CPM5_PCIE_ATTR | 0x00FCE88000 | CPM5 PCIe Attributes (program with design tools) (aka PCIEA5_ATTRIB), CPM5 PCIe Controller 1 Attributes |
CPM5_PCIE1_CSR | CPM5_PCIE_CSR | 0x00FCE80000 | CPM5 PCIe Control and Status, CPM5 PCIe Controller 1 Control and Status |
CPM5_SLCR | CPM5_SLCR | 0x00FCDD0000 | CPM5 SLCR Registers, CPM5 System-level Control Registers |
CPM5_SLCR_SECURE | CPM5_SLCR_SECURE | 0x00FCDE0000 | CPM5 SLCR Secure Registers, CPM5 Secure System-level Control Registers |
CPM_PCSR | CPM_PCSR | 0x00FCFF0000 | CPM4 and CPM5 Control and Status Registers |
CRF | CRF | 0x00FD1A0000 | FPD Clock and Resets Controllers |
CRL | CRL | 0x00FF5E0000 | LPD Clock and Resets Controllers |
CRP | CRP | 0x00F1260000 | PMC Clock and Resets Controllers, ClkMon Controller |
DBG_APU0_CTI | DBG_A720_CTI | 0x00F0D10000 | CoreSight APU core 0 Cross-trigger Interface |
DBG_APU0_DBG | DBG_A720_DBG | 0x00F0D00000 | CoreSight APU core 0 Built-in Debug Logic |
DBG_APU0_ETM | DBG_A720_ETM | 0x00F0D30000 | CoreSight APU core 0 Generate Trace |
DBG_APU0_PMU | DBG_A720_PMU | 0x00F0D20000 | CoreSight APU core 0 Processor Performance Profile |
DBG_APU1_CTI | DBG_A721_CTI | 0x00F0D50000 | CoreSight APU core 1 Cross-trigger Interface |
DBG_APU1_DBG | DBG_A721_DBG | 0x00F0D40000 | CoreSight APU core 1 Built-in Debug Logic |
DBG_APU1_ETM | DBG_A721_ETM | 0x00F0D70000 | CoreSight APU core 1 Generate Trace |
DBG_APU1_PMU | DBG_A721_PMU | 0x00F0D60000 | CoreSight APU core 1 Processor Performance Profile |
DBG_APU_CTI | DBG_CTI | 0x00F0CA0000 | CoreSight Cross-trigger Inteface, Dual APU |
DBG_APU_ELA | DBG_ELA_128 | 0x00F0C60000 | CoreSight Embedded 128 Logic Analyser, Dual APU |
DBG_APU_ETF | DBG_ETF_4K | 0x00F0C30000 | CoreSight Embedded 4K Trace FIFO, Dual APU |
DBG_APU_FUN | DBG_FUNNEL_2P | 0x00F0C20000 | CoreSight Merge Two Trace Streams to ATB, Dual APU |
DBG_CPM_CTI | DBG_CTI | 0x00F0FD0000 | CoreSight Cross-trigger Inteface, CPM CTI 2D |
DBG_CPM_ELA2A | DBG_ELA_256 | 0x00F0F40000 | CoreSight Embedded 256 Logic Analyser, CPM PCIe 0 ELA 2A |
DBG_CPM_ELA2B | DBG_ELA_256 | 0x00F0F50000 | CoreSight Embedded 256 Logic Analyser, CPM PCIe 1 ELA 2B |
DBG_CPM_ELA2C | DBG_ELA_256 | 0x00F0F60000 | CoreSight Embedded 256 Logic Analyser, CPM PCIe 2 ELA 2C |
DBG_CPM_ELA2D | DBG_ELA_256 | 0x00F0F70000 | CoreSight Embedded 256 Logic Analyser, CPM PCIe L2 ELA 2D |
DBG_CPM_ELA_CTI | DBG_CTI | 0x00F0FA0000 | CoreSight Cross-trigger Inteface, CPM ELA CTI 2A |
DBG_CPM_FUN | DBG_FUNNEL_2P | 0x00F0F20000 | CoreSight Merge Two Trace Streams to ATB, CPM |
DBG_CPM_ROM | DBG_CPM_ROM | 0x00F0F00000 | CoreSight CPM ROM |
DBG_FPD_CTI | DBG_CTI | 0x00F0BD0000 | CoreSight Cross-trigger Inteface, FPD CTI 1D |
DBG_FPD_ETF | DBG_ETF_32K | 0x00F0B30000 | CoreSight Embedded 32K Trace FIFO, FPD |
DBG_FPD_ETR | DBG_ETR | 0x00F0B50000 | CoreSight Enable Local Trace Buffer, FPD |
DBG_FPD_FUN | DBG_FUNNEL_6P | 0x00F0B20000 | CoreSight Merge Six Trace Streams to ATB |
DBG_FPD_GPR | DBG_GPR_2P | 0x00F0B10000 | CoreSight GPR 2P |
DBG_FPD_PSPL_CTI | DBG_CTI | 0x00F0BC0000 | CoreSight Cross-trigger Inteface, FPD PS-PL and PL-PS CTI 1C |
DBG_FPD_REPL | DBG_REPLICATOR | 0x00F0B40000 | CoreSight Replicates ATB Data Stream |
DBG_FPD_ROM | DBG_FPD_ROM | 0x00F0B00000 | CoreSight FPD ROM |
DBG_FPD_SOC_CTI | DBG_CTI | 0x00F0BB0000 | CoreSight Cross-trigger Inteface, FPD SoC CTI 1B |
DBG_FPD_TPIU | DBG_TPIU | 0x00F0B60000 | CoreSight Trace Port Interface Unit |
DBG_LPD_CTI | DBG_CTI | 0x00F09D0000 | CoreSight Cross-trigger Inteface, LPD SoC |
DBG_LPD_FUN | DBG_FUNNEL_5P | 0x00F0920000 | CoreSight Merge Five Trace Streams to ATB |
DBG_LPD_GPR | DBG_GPR_3P | 0x00F0910000 | CoreSight GPR 3P, LPD |
DBG_LPD_ROM | DBG_LPD_ROM | 0x00F0900000 | CoreSight LPD ROM |
DBG_PMC_CTI | DBG_CTI | 0x00F08D0000 | CoreSight Cross-trigger Inteface, PMC |
DBG_PMC_GPR | DBG_GPR_1P | 0x00F0810000 | CoreSight GPR 1P, PMC |
DBG_PMC_ROM | DBG_PMC_ROM | 0x00F0800000 | CoreSight PMC ROM |
DBG_RPU0_CTI | DBG_CTI | 0x00F0A10000 | CoreSight Cross-trigger Inteface, RPU core 0 |
DBG_RPU0_DBG | DBG_R50_DBG | 0x00F0A00000 | CoreSight RPU core 0 Built-in Debug Logic |
DBG_RPU0_ETM | DBG_R50_ETM | 0x00F0A30000 | CoreSight RPU core 0 Generate Trace |
DBG_RPU1_CTI | DBG_CTI | 0x00F0A50000 | CoreSight Cross-trigger Inteface, RPU core 1 |
DBG_RPU1_DBG | DBG_R51_DBG | 0x00F0A40000 | CoreSight RPU core 1 Built-in Debug Logic |
DBG_RPU1_ETM | DBG_R51_ETM | 0x00F0A70000 | CoreSight RPU core 1 Generate Trace |
DBG_STM | DBG_STM | 0x00F0B70000 | CoreSight System Trace Module |
DBG_TSG_RW | DBG_TSG_RW | 0x00F0990000 | CoreSight Time Stamp with read/write Interface |
DPC_AURORA | DPC_AURORA_CSR | 0x00FF9C0000 | Aurora Debug Interface (aka AURORA) |
DPC_DMA_CSR | DPC_DMA_CSR | 0x00FE5F0000 | Debug Port Controller DMA (aka HSDP_DMA) |
FPD_CCI_CORE | FPD_CCI_CORE | 0x00FD000000 | FPD CCI500 Core (aka CCI500) |
FPD_CCI_CSR | FPD_CCI_CSR | 0x00FD5E0000 | FPD CCI Wrapper (aka CCI_REG) |
FPD_INT_CSR | FPD_INT_CSR | 0x00FD370000 | FPD Interconnect Control and Status (aka INT_FPD_REGS) |
FPD_INT_GPV | FPD_INT_GPV | 0x00FD700000 | FPD Interconnect GPV |
FPD_SLCR | FPD_SLCR | 0x00FD610000 | FPD System Control Registers |
FPD_SLCR_SECURE | FPD_SLCR_SECURE | 0x00FD690000 | FPD System Control Registers (secure) |
FPD_SMMU_CSR | FPD_SMMU_CSR | 0x00FD5F0000 | FPD System Memory Management Unit (CSRs) (aka SMMU_CSR) |
FPD_SMMU_TCU | FPD_SMMU_TCU | 0x00FD800000 | FPD System Memory Management TCU (secure) (aka SMMU500) |
FPD_SWDT | SWDT | 0x00FD4D0000 | PS System Watchdog Timer (aka WWDT), (aka SWDT1) |
FPD_XMPU | XMPU | 0x00FD390000 | Xilinx Memory Protection Unit |
GEM0 | GEM | 0x00FF0C0000 | Gigabit Ethernet MAC, Controller 0 |
GEM1 | GEM | 0x00FF0D0000 | Gigabit Ethernet MAC, Controller 1 |
IPI | IPI | 0x00FF300000 | PS Inter-Processor Interrupts |
LPD_DMA_CH0 | PS_DMA | 0x00FFA80000 | LPD General Purpose DMA (aka ZDMA), LPD Ch 0 |
LPD_DMA_CH1 | PS_DMA | 0x00FFA90000 | LPD General Purpose DMA (aka ZDMA), LPD Ch 1 |
LPD_DMA_CH2 | PS_DMA | 0x00FFAA0000 | LPD General Purpose DMA (aka ZDMA), LPD Ch 2 |
LPD_DMA_CH3 | PS_DMA | 0x00FFAB0000 | LPD General Purpose DMA (aka ZDMA), LPD Ch 3 |
LPD_DMA_CH4 | PS_DMA | 0x00FFAC0000 | LPD General Purpose DMA (aka ZDMA), LPD Ch 4 |
LPD_DMA_CH5 | PS_DMA | 0x00FFAD0000 | LPD General Purpose DMA (aka ZDMA), LPD Ch 5 |
LPD_DMA_CH6 | PS_DMA | 0x00FFAE0000 | LPD General Purpose DMA (aka ZDMA), LPD Ch 6 |
LPD_DMA_CH7 | PS_DMA | 0x00FFAF0000 | LPD General Purpose DMA (aka ZDMA), LPD Ch 7 |
LPD_GPIO | LPD_GPIO | 0x00FF0B0000 | LPD GPIO I/O Peripheral Controller (aka PS_GPIO) |
LPD_I2C0 | PS_I2C | 0x00FF020000 | LPD I2C I/O Peripheral Controller, Controller 0 |
LPD_I2C1 | PS_I2C | 0x00FF030000 | LPD I2C I/O Peripheral Controller, Controller 1 |
LPD_INT_CSR | LPD_INT_CSR | 0x00FE600000 | LPD Interconnect Config (aka INTLPD_CONFIG) |
LPD_INT_GPV | LPD_INT_GPV | 0x00FE400000 | LPD Interconnect GPV (aka INT_LPD_GPV) |
LPD_IOP_INT_GPV | LPD_IOP_INT_GPV | 0x00FE000000 | LPD IOP Interconnect GPV (aka LPD_INT_IOU_GPV) |
LPD_IOP_SLCR | LPD_IOP_SLCR | 0x00FF080000 | LPD IOP System-level Control Registers (aka LPD_IOU_SLCR) |
LPD_IOP_SLCR_SECURE | LPD_IOP_SLCR_SECURE | 0x00FF0A0000 | LPD IOP System-level Control Registers (secure) (aka LPD_IOU_SECURE_SLCR) |
LPD_SLCR | LPD_SLCR | 0x00FF410000 | LPD System-level Control Registers |
LPD_SLCR_SECURE | LPD_SLCR_SECURE | 0x00FF510000 | LPD System-level Control Registers (secure) |
LPD_SWDT | SWDT | 0x00FF120000 | PS System Watchdog Timer (aka WWDT), (aka SWDT0) |
LPD_XPPU | XPPU | 0x00FF990000 | Xilinx Peripheral Protection Unit, LPD |
OCM_CSR | OCM_CSR | 0x00FF960000 | OnChip Memory Control and Status (aka OCM) |
OCM_XMPU | XMPU | 0x00FF980000 | Xilinx Memory Protection Unit, OCM |
OSPI | OSPI | 0x00F1010000 | Octal-SPI Flash Memory Controller |
PLM_RTCA | PLM_RTCA | 0x00F2014000 | PLM Runtime Configuration Area (RTCA) in PMC RAM |
PL_ACELITE_FPD_CSR | PL_AFI_CSR | 0x00FD380000 | PL to PS AMBA FIFO Interface Control, (aka S_AXI_HPC and AFIFM2) |
PL_AXI_FPD_CSR | PL_AFI_CSR | 0x00FD360000 | PL to PS AMBA FIFO Interface Control, (aka S_AXI_HP and AFIFM0) |
PL_AXI_LPD_CSR | PL_AFI_CSR | 0x00FF9B0000 | PL to PS AMBA FIFO Interface Control, (aka AFIFM4) |
PMC_ANLG | PMC_ANLG | 0x00F1160000 | PMC Misc Analog Control |
PMC_DMA0_CSR | PMC_DMA_CSR | 0x00F11C0000 | PMC DMA Unit (aka PMCDMA), Controller 0 |
PMC_DMA1_CSR | PMC_DMA_CSR | 0x00F11D0000 | PMC DMA Unit (aka PMCDMA), Controller 1 |
PMC_EFUSE_CACHE | PMC_EFUSE_CACHE | 0x00F1250000 | PMC eFuse Cache Control |
PMC_EFUSE_CTRL | PMC_EFUSE_CTRL | 0x00F1240000 | PMC eFuse Controller |
PMC_GLOBAL | PMC_GLOBAL | 0x00F1110000 | PMC Global, Private, Errors, GIC Proxy, PUF registers |
PMC_GPIO | PMC_GPIO | 0x00F1020000 | PMC GPIO Controller |
PMC_I2C | PMC_I2C | 0x00F1000000 | PMC I2C Controller |
PMC_INT_CSR | PMC_INT_CSR | 0x00F1330000 | PMC Interconnect (aka PMC_INT_REGS), APB interface to program all PMC NIU reset and isolation |
PMC_INT_GPV | PMC_INT_GPV | 0x00F1320000 | PMC Main Interconnect GPV (aka PMC_MAIN_GPV) |
PMC_IOP_INT_GPV | PMC_IOP_INT_GPV | 0x00F1080000 | PMC IOP Interconnect GPV (aka PMC_INT_IOU_GPV) |
PMC_IOP_SLCR | PMC_IOP_SLCR | 0x00F1060000 | PMC I/O Peripheral Control and Status (aka PMC_IOU_SLCR) |
PMC_IOP_SLCR_SECURE | PMC_IOP_SLCR_SECURE | 0x00F1070000 | PMC I/O Peripheral Control and Status (secure) (aka PMC_IOU_SECURE_SLCR) |
PMC_JTAG_CSR | PMC_JTAG_CSR | 0x00F11A0000 | PMC TAP Controller (aka PMC_TAP) |
PMC_LOCAL | PMC_LOCAL | 0x00F0040000 | PMC Local Registers |
PMC_RAM_CSR | PMC_RAM_CSR | 0x00F2000000 | PMC RAM Configuration |
PMC_RTC | PMC_RTC | 0x00F12A0000 | PMC Real-Time Clock (aka RTC) |
PMC_SBI_CSR | PMC_SBI_CSR | 0x00F1220000 | PMC Slave Boot Interface |
PMC_SYSMON_CSR | PMC_SYSMON_CSR | 0x00F1270000 | PMC System Monitor (aka ams_root) |
PMC_XMPU | XMPU | 0x00F12F0000 | Xilinx Memory Protection Unit |
PMC_XPPU | XPPU | 0x00F1310000 | Xilinx Peripheral Protection Unit, PMC IOP |
PMC_XPPU_NPI | XPPU | 0x00F1300000 | Xilinx Peripheral Protection Unit, PMC NPI |
PPU_DCACHE_CTRL | MB_RAM_ECC_CTRL | 0x00F0282000 | MicroBlaze RAM ECC Control, PPU |
PPU_ICACHE_CTRL | MB_RAM_ECC_CTRL | 0x00F0281000 | MicroBlaze RAM ECC Control, PPU |
PPU_IOMODULE | MB_IOMODULE | 0x00F0280000 | MicroBlaze IO Module, PPU |
PPU_MDM | MB_MDM | 0x00F0310000 | MicroBlaze Debug Module, PPU |
PPU_TMR_INJECT | MB_TMR_INJECT | 0x00F0284000 | MicroBlaze Error Injection, PPU |
PPU_TMR_MANAGER | MB_TMR_MANAGER | 0x00F0283000 | MicroBlaze Redundancy Manager, PPU |
PPU_TMR_TRACE | MB_TMR_TRACE | 0x00F0300000 | MicroBlaze Trace Debug, PPU |
PSM_DCACHE_ECC | MB_RAM_ECC_CTRL | 0x00FFCB0000 | MicroBlaze RAM ECC Control, PSM |
PSM_GLOBAL | PSM_GLOBAL | 0x00FFC90000 | PSM Global, Error, GIC Proxy registers (aka PSM_GLOBAL_REG) |
PSM_ICACHE_ECC | MB_RAM_ECC_CTRL | 0x00FFCA0000 | MicroBlaze RAM ECC Control, PSM |
PSM_INT_CSR | PSM_INT_CSR | 0x00FFC9E000 | PSM Interconnect Registers, (was part of PSM_GLOBAL_REG) |
PSM_INT_GPV | PSM_INT_GPV | 0x00FFC9F000 | PSM Interconnect GPV (aka INT_PSM_STRUCT) |
PSM_IOMODULE | MB_IOMODULE | 0x00FFC80000 | MicroBlaze IO Module, PSM |
PSM_LOCAL | PSM_LOCAL | 0x00FFC88000 | PSM Local Registers (aka PSM_LOCAL_REG) |
PSM_MDM | MB_MDM | 0x00FFCF0000 | MicroBlaze Debug Module, PSM |
PSM_TMR_INJECT | MB_TMR_INJECT | 0x00FFCD0000 | MicroBlaze Error Injection, PSM |
PSM_TMR_MANAGER | MB_TMR_MANAGER | 0x00FFCC0000 | MicroBlaze Redundancy Manager, PSM |
PSM_TMR_TRACE | MB_TMR_TRACE | 0x00FFCE0000 | MicroBlaze Trace Debug, PSM |
QSPI | QSPI | 0x00F1030000 | Quad-SPI Flash Memory Controller |
RPU_DUAL_CSR | RPU_DUAL_CSR | 0x00FF9A0000 | RPU MPCore Dual Processor Control |
RPU_GIC_PL390 | RPU_GIC_PL390 | 0x00F9000000 | RPU GIC Interrupt Controller (aka PL390) |
SCNTR | SCNTR | 0x00FF130000 | PS System Counter (read only) (aka IOU_SCNTR) |
SCNTR_SECURE | SCNTR_SECURE | 0x00FF140000 | PS System Counter (secure; read/write) (aka IOU_SCNTRS) |
SD_eMMC0 | SD_eMMC | 0x00F1040000 | SD_eMMC Flash Interface Controller (aka SDIO), Controller 0 |
SD_eMMC1 | SD_eMMC | 0x00F1050000 | SD_eMMC Flash Interface Controller (aka SDIO), Controller 1 |
SPI0 | SPI | 0x00FF040000 | SPI I/O Peripheral Controller, Controller 0 |
SPI1 | SPI | 0x00FF050000 | SPI I/O Peripheral Controller, Controller 1 |
TTC0 | TTC | 0x00FF0E0000 | PS Triple Timer Counter, Instance 0 |
TTC1 | TTC | 0x00FF0F0000 | PS Triple Timer Counter, Instance 1 |
TTC2 | TTC | 0x00FF100000 | PS Triple Timer Counter, Instance 2 |
TTC3 | TTC | 0x00FF110000 | PS Triple Timer Counter, Instance 3 |
UART0 | UART | 0x00FF000000 | UART SBSA, Controller 0 |
UART1 | UART | 0x00FF010000 | UART SBSA, Controller 1 |
USB2_CSR | USB_CSR | 0x00FF9D0000 | USB v2.0 Control and Status (aka USB2_REGS) |
USB2_XHCI | USB_XHCI | 0x00FE200000 | USB v2.0 XHCI (subset of USB 3.0) |
XRAM_CTRL0 | XRAM_CTRL | 0x00FF8E0000 | XRAM Control and Status, XRAM Bank0 register space |
XRAM_CTRL1 | XRAM_CTRL | 0x00FF8F0000 | XRAM Control and Status, XRAM Bank1 register space |
XRAM_CTRL2 | XRAM_CTRL | 0x00FF900000 | XRAM Control and Status, XRAM Bank2 register space |
XRAM_CTRL3 | XRAM_CTRL | 0x00FF910000 | XRAM Control and Status, XRAM Bank3 register space |
XRAM_INT_GPV | XRAM_INT_GPV | 0x00FF940000 | XRAM Global Programmer View (aka XRAM_GPV) |
XRAM_SLCR | XRAM_SLCR | 0x00FF950000 | XRAM System-level Registers |
XRAM_XMPU0 | XMPU | 0x00FF930000 | Xilinx Memory Protection Unit, XRAM Bank 0 |
XRAM_XMPU1 | XMPU | 0x00FF934000 | Xilinx Memory Protection Unit, XRAM Bank 1 |
XRAM_XMPU2 | XMPU | 0x00FF938000 | Xilinx Memory Protection Unit, XRAM Bank 2 |
XRAM_XMPU3 | XMPU | 0x00FF93C000 | Xilinx Memory Protection Unit, XRAM Bank 3 |