Overview

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3
Overview

Overview

This reference manual provides details of all the memory-mapped registers in Versal Adaptive SoCs.

Throughout this manual, the names of registers and register bit fields used match those given in the hardware. They are called the hardware names. The C header files delivered with this product define register and bit field names for easy use in the software code. In some cases, the software names are different from the hardware names. This manual includes software names where they differ from hardware names:

  • Software Module Name: This is included in the module introduction section and is named Software Name.
  • Software Register Name: This is included in the detailed register description and is also named Software Name.
  • Software Bit field Name: These are included in the register bit field tables in the Field Name column. These names follow the hardware field name and are in parentheses.

Note: If a software name does not exist in the C header files or if it exists but is the same as the hardware name, it is not included in this reference manual and the above fields are not present.

The software register name is:
<software module name>_<software register name>_<optional suffix>. One common suffix used for register names is “OFFSET”, which provides the OFFSET address of the register from the base address for the module.

The software bit field name is:
<software module name>_<software register name>_<software bit field name>_<optional suffix>. One common suffix used for bit field names is “MASK”, which is useful when extracting the bit field of interest from the full register.

Introduction to Versal Adaptive SoCs

Versal™ Adaptive SoCs combine Scalar Engines, Adaptable Engines, and Intelligent Engines with leading-edge memory and interfacing technologies to deliver powerful heterogeneous acceleration for any application. Most importantly, Versal Adaptive SoC hardware and software are targeted for programming and optimization by data scientists and software and hardware developers. Versal Adaptive SoCs are enabled by a host of tools, software, libraries, IP, middleware, and frameworks to enable all industry-standard design flows.

Built on the TSMC 7 nm FinFET process technology, the Versal portfolio is the first platform to combine software programmability and domain-specific hardware acceleration with the adaptability necessary to meet today's rapid pace of innovation. The portfolio includes six series of devices uniquely architected to deliver scalability and AI inference capabilities for a host of applications across different markets—from cloud—to networking—to wireless communications—to edge computing and endpoints.

The Versal architecture combines different engine types with a wealth of connectivity and communication capability and a network on chip (NoC) to enable seamless memory-mapped access to the full height and width of the device. Intelligent Engines are SIMD VLIW AI Engines for adaptive inference and advanced signal processing compute, and DSP Engines for fixed point, floating point, and complex MAC operations. Adaptable Engines are a combination of programmable logic blocks and memory, architected for high-compute density. Scalar Engines, including Arm® Cortex™-A72 and Cortex-R5F processors, allow for intensive compute tasks.

The Versal AI Core series delivers breakthrough AI inference acceleration with AI Engines that deliver over 100x greater compute performance than current server-class of CPUs. This series is designed for a breadth of applications, including cloud for dynamic workloads and network for massive bandwidth, all while delivering advanced safety and security features. AI and data scientists, as well as software and hardware developers, can all take advantage of the highcompute density to accelerate the performance of any application.

The Versal Prime series is the foundation and the mid-range of the Versal platform, serving the broadest range of uses across multiple markets. These applications include 100G to 200G networking equipment, network and storage acceleration in the Data Center, communications test equipment, broadcast, and aerospace & defense. The series integrates mainstream 58G transceivers and optimized I/O and DDR connectivity, achieving low-latency acceleration and performance across diverse workloads.

Navigating Content by Design Process

Xilinx® documentation is organized around a set of standard design processes to help you find relevant content for your current development task. This document covers the following design processes:

  • System and Solution Planning: Identifying the components, performance, I/O, and data transfer requirements at a system level. Includes application mapping for the solution to PS, PL, and AI Engine.
  • Embedded Software Development: Creating the software platform from the hardware platform and developing the application code using the embedded CPU. Also covers XRT and Graph APIs.
  • Board System Design: Designing a PCB through schematics and board layout. Also involves power, thermal, and signal integrity considerations.

Inclusive Terminology

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