PCIeBar2AXIBar_0_PF1_L (CPM4_DMA_ATTR) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

PCIeBar2AXIBar_0_PF1_L (CPM4_DMA_ATTR) Register Description

Register NamePCIeBar2AXIBar_0_PF1_L
Relative Address0x00000002A0
Absolute Address 0x00FCA702A0 (CPM4_DMA_ATTR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionBits[63:12] Bar Translation for PF1 BAR0

This register should only be written to during reset of the PCIe block Alternate register name: attr_dma_pciebar2axibar_0_pf1_l

PCIeBar2AXIBar_0_PF1_L (CPM4_DMA_ATTR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr19:0rwNormal read/write0x0Bits[63:12] Bar Translation for PF1 BAR0