PCIeBar2AXIBar_5_Wr_Cache_PF1 (CPM4_DMA_ATTR) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

PCIeBar2AXIBar_5_Wr_Cache_PF1 (CPM4_DMA_ATTR) Register Description

Register NamePCIeBar2AXIBar_5_Wr_Cache_PF1
Relative Address0x0000000340
Absolute Address 0x00FCA70340 (CPM4_DMA_ATTR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionARCACHE value for PF1 BAR5 writes

This register should only be written to during reset of the PCIe block Alternate register name: attr_dma_pciebar2axibar_5_wr_cache_pf1

PCIeBar2AXIBar_5_Wr_Cache_PF1 (CPM4_DMA_ATTR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr 3:0rwNormal read/write0x0ARCACHE value for PF1 BAR5 writes