PF0_Wr_Cache (CPM4_DMA_ATTR) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

PF0_Wr_Cache (CPM4_DMA_ATTR) Register Description

Register NamePF0_Wr_Cache
Relative Address0x000000084C
Absolute Address 0x00FCA7084C (CPM4_DMA_ATTR)
Width32
TyperwNormal read/write
Reset Value0x00000000
Descriptionmultiq AIXMM_AWCACHE setting

This register should only be written to during reset of the PCIe block Alternate register name: attr_dma_pf0_wr_cache

PF0_Wr_Cache (CPM4_DMA_ATTR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr 3:0rwNormal read/write0x0multiq AIXMM_AWCACHE setting