PWRCTL (APU_DUAL_CSR) Register Description
| Register Name | PWRCTL |
|---|---|
| Relative Address | 0x0000000090 |
| Absolute Address | 0x00FD5C0090 (APU_DUAL_CSR) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Power Control Register |
PWRCTL (APU_DUAL_CSR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| CLREXMONREQ | 17 | rwNormal read/write | 0x0 | Drives the A72MP CLREXMONREQ signal that indicates the clearing of the external global exclusive monitor request. When this signal is asserted, it acts as a WFE wake-up event to all the processors in the MPCore device. For details, refer to ARM Cortex-A72 MPCore Processor Technical Reference Manual. |
| L2FLUSHREQ | 16 | rwNormal read/write | 0x0 | Drives the A72MP L2FLUSHREQ signal that makes L2 hardware flush request. For details, refer to ARM Cortex-A72 MPCore Processor Technical Reference Manual. |
| CPUPWRDWNREQ | 1:0 | rwNormal read/write | 0 | Enables the A72MP STANDBYWFI signals to also function as power-down request signals for CPUn power islands. Regardless of this field, the STANDBYWFI status is always sent to the PSM. The upper bit is for CPU 1 power island; the lower bit is for CPU 0 power island. |