PWRSTAT (APU_DUAL_CSR) Register Description
| Register Name | PWRSTAT |
|---|---|
| Relative Address | 0x0000000094 |
| Absolute Address | 0x00FD5C0094 (APU_DUAL_CSR) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x00000000 |
| Description | Power Status Register |
PWRSTAT (APU_DUAL_CSR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| CLREXMONACK | 17 | roRead-only | 0x0 | Receives the A72MP CLREXMONACK signal value that indicates CLREXMONREQ is acknowledged. For details, refer to ARM Cortex-A72 MPCore Processor Technical Reference Manual. |
| L2FLUSHDONE | 16 | roRead-only | 0x0 | Receives the A72MP L2FLUSHDONE signal value that indicates L2 hardware flush is done. For details, refer to ARM Cortex-A72 MPCore Processor Technical Reference Manual. |
| DBGNOPWRDWN | 1:0 | roRead-only | 0x0 | Receives the A72MP DBGNOPWRDWN signal value that indicates power must not be removed from the CPUn island. For details, refer to ARM Cortex-A72 MPCore Processor Technical Reference Manual. The upper bit is for CPU 1 power island; the lower bit is for CPU 0 power island. |