RST_L2_1 (CPM4_CRX) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

RST_L2_1 (CPM4_CRX) Register Description

Register NameRST_L2_1
Relative Address0x000000031C
Absolute Address 0x00FCA0031C (CPM4_CRX)
Width 1
TyperwNormal read/write
Reset Value0x00000001
DescriptionReset for L2 block (includes CHI RegSlice and interrupt synchronization)

This reset must be released even if CHI interface is used with L2 bypassed.

RST_L2_1 (CPM4_CRX) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
RESET 0rwNormal read/write0x1block will be reset when asserted 1