RVBARADDR1L (APU_DUAL_CSR) Register Description
| Register Name | RVBARADDR1L |
|---|---|
| Relative Address | 0x0000000048 |
| Absolute Address | 0x00FD5C0048 (APU_DUAL_CSR) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0xFFFF0000 |
| Description | Reset Vector Base Address |
RVBARADDR1L (APU_DUAL_CSR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| ADDR | 31:2 | rwNormal read/write | 0x3FFFC000 | Drives the A72MP RVBARADDR1[31:2] signals that determine the Reset Vector Base Address for executing in AArch64 state. For details, refer to ARM Cortex-A72 MPCore Processor Technical Reference Manual. This register is for CPU core 1. |