SNOOP_CTRL (APU_DUAL_CSR) Register Description
| Register Name | SNOOP_CTRL |
|---|---|
| Relative Address | 0x0000000080 |
| Absolute Address | 0x00FD5C0080 (APU_DUAL_CSR) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Snoop Control Register |
SNOOP_CTRL (APU_DUAL_CSR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| ACE_inact | 4 | rwNormal read/write | 0x0 | Drives the A72MP ACINACTM signal. When this signal is high, the snoop address channel stops accepting requests by deasserting ACREADYM. Snoop requests that were accepted before deasserting ACREADYM are serviced. For details, refer to ARM Cortex-A72 MPCore Processor Technical Reference Manual. |
| ACP_inact | 0 | rwNormal read/write | 0x0 | This bit is ORed with the "PLPSACPINACT" signal from PL, then drives the A72MP AINACTS signal. When this signal is high, the ACP stops accepting requests by deasserting ARREADYS and AWREADYS. For details, refer to ARM Cortex-A72 MPCore Processor Technical Reference Manual. |