SW_Reset (CANFD) Register Description
| Register Name | SW_Reset |
|---|---|
| Relative Address | 0x0000000000 |
| Absolute Address |
0x00FF060000 (CANFD0) 0x00FF070000 (CANFD1) |
| Width | 2 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Software Reset and Enable Control |
Writing to the Software Reset Register (SW_Reset) places the CAN controller in Configuration mode. Once in Configuration mode, the controller drives recessive bits on the bus line and does not transmit or receive messages. Reset State: * SW_Reset [CEN] and [SRST] = 0 * SR [CONFIG] = 1 Transfer Layer Configuration registers should only be changed when SW_Reset [CEN] = 0. If the [CEN] bit is changed during operation, it is recommended to reset the controller. Mode Select Register bits, except [SLEEP] and [SBR], should only be changed when [CEN] = 0. Software Driver name: XCANFD_SRR Alternate register name: Software_Reset_Register
SW_Reset (CANFD) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| CEN | 1 | rwNormal read/write | 0x0 | Controller Enable, read-write: 0: controller in Configuration mode. 1: controller in loopback, sleep, snoop, or normal mode; see Mode_Select [LBACK], [SLEEP], and [SNOOP] bits to determine the precise state. Note: The combination of settings for Mode_Select [LBACK], [SLEEP], and [SNOOP] are shown in the CAN Controller Modes table of the TRM. Note: If the [CEN] bit is changed during the controllers operation, it is recommended to reset the controller so that operations start afresh. Note: Post reset when [CEN] = 1, the controller exits configuration mode after detecting 11 consecutive recessive bits on the CAN bus. |
| SRST | 0 | woWrite-only | 0x0 | Controller Reset, write-only: 0: not reset. 1: held in reset. Note: If a 1 is written to this bit, all the controller configuration registers (including the SW_Reset) are reset. Note: Reads to this bit always return a 0. |