Spare_1_L (CPM4_DMA_ATTR) Register Description
| Register Name | Spare_1_L |
|---|---|
| Relative Address | 0x0000000078 |
| Absolute Address | 0x00FCA70078 (CPM4_DMA_ATTR) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Bits,Field,Recommended setting,Description [31:21],brdg_slv_pasid_offset[10:0],11h0,Pasid index offset[10:0] for bridge slave requests. Pasid index offset [11] is defined in the attr_dma_1_h attribute register. [20],Reserved,1h0,Reserved [19],axis_h2c_ext_cmp_en,1h1,"QDMA set to 0x1. Use external signal to indicating h2c stream packet is complete, for the purpose of issueing writeback and interrupts."[18],Reserved,1h0,Reserved [17],dma_bar_ext_en,1h1,"Recommended setting: 1b1. If set, enable the DMA PCIe bar aperture to AXI MM."[16:12],tcp_timeout_exp[4:0],5h12,"Recommended setting: 5h12. Exponential timer for TRQ completion timeout 2^exp[4:0], 0 = disabled. "[11],brdg_slv_pasid_en,1h0,Enable PASID for the Bridge. [10],system_id_ovr,1h0,"If set, the system id register will show the value of the system_id attribute"[9:0],system_id[15:6],10h0,System ID csr. Value that will be read from the dma global system_id register if the system_id_ovr attribute bit is set. System ID csr[5:0] defined in attr_dma_0_h attribute register. |
This register should only be written to during reset of the PCIe block Alternate register name: attr_dma_spare_1_l
Spare_1_L (CPM4_DMA_ATTR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| attr | 31:0 | rwNormal read/write | 0x0 | Bits,Field,Recommended setting,Description [31:21],brdg_slv_pasid_offset[10:0],11h0,Pasid index offset[10:0] for bridge slave requests. Pasid index offset [11] is defined in the attr_dma_1_h attribute register. [20],Reserved,1h0,Reserved [19],axis_h2c_ext_cmp_en,1h1,"QDMA set to 0x1. Use external signal to indicating h2c stream packet is complete, for the purpose of issueing writeback and interrupts."[18],Reserved,1h0,Reserved [17],dma_bar_ext_en,1h1,"Recommended setting: 1b1. If set, enable the DMA PCIe bar aperture to AXI MM."[16:12],tcp_timeout_exp[4:0],5h12,"Recommended setting: 5h12. Exponential timer for TRQ completion timeout 2^exp[4:0], 0 = disabled. "[11],brdg_slv_pasid_en,1h0,Enable PASID for the Bridge. [10],system_id_ovr,1h0,"If set, the system id register will show the value of the system_id attribute"[9:0],system_id[15:6],10h0,System ID csr. Value that will be read from the dma global system_id register if the system_id_ovr attribute bit is set. System ID csr[5:0] defined in attr_dma_0_h attribute register. |