Spare_2_H (CPM4_DMA_ATTR) Register Description
Register Name | Spare_2_H |
---|---|
Relative Address | 0x0000000084 |
Absolute Address | 0x00FCA70084 (CPM4_DMA_ATTR) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | Bits,Field,Recommended setting,Description [31:22],Reserved,10h0,Reserved [21],cfg_space_delay_en,1h0,"If set, enable Bridge register to control config space enable in the EP mode"[20:0],misc_cap[31:11],21h0,"Used to advertise configured capabilities and version information to software. Accessible in DMA_GLBL2_MISC_CAP register. Bits [10:0] defined in previous attribute register. misc_cap[31:16] RTL_VERSION misc_cap[15:11]: Reserved 5h0 |
This register should only be written to during reset of the PCIe block Alternate register name: attr_dma_spare_2_h
Spare_2_H (CPM4_DMA_ATTR) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
attr | 31:0 | rwNormal read/write | 0x0 | Bits,Field,Recommended setting,Description [31:22],Reserved,10h0,Reserved [21],cfg_space_delay_en,1h0,"If set, enable Bridge register to control config space enable in the EP mode"[20:0],misc_cap[31:11],21h0,"Used to advertise configured capabilities and version information to software. Accessible in DMA_GLBL2_MISC_CAP register. Bits [10:0] defined in previous attribute register. misc_cap[31:16] RTL_VERSION misc_cap[15:11]: Reserved 5h0 |