Spare_3_L (CPM4_DMA_ATTR) Register Description
| Register Name | Spare_3_L |
|---|---|
| Relative Address | 0x0000000088 |
| Absolute Address | 0x00FCA70088 (CPM4_DMA_ATTR) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Bits,Field,Recommended setting,Description [31:17],Reserved,15h0,Reserved [16:13],qinv_cnt_limit,4h1,"Affects QDMA only. If qinv_limit_en is set, this is the limit of qinv from dsc engine through c2h st pfch_evt_fifo that is allowed"[12],qinv_limit_en,4h1,"Affects QDMA only. If set, limit the number of qinvalidation in the pipe from dsc engine through C2H ST pfch_evt_fifo."[11],qinv_arb_stall,1h0,"Affects QDMA only. If set, allow descriptor fetching to continue even if tm_dsc_sts is full."[10],brdg_rro_en,1h0,"If set, enable relaxed ordering for all bridge slave reads to pcie."[9],Reserved,1h0,Reserved [8],pcie_mrs_reg_en,1h0,"If set, pcie max read size used will be defined by register"[7],pcie_mpl_reg_en,1h0,"If set, pcie max payload used will be define by register"[6:0],Reserved,7h0,Reserved |
This register should only be written to during reset of the PCIe block Alternate register name: attr_dma_spare_3_l
Spare_3_L (CPM4_DMA_ATTR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| attr | 31:0 | rwNormal read/write | 0x0 | Bits,Field,Recommended setting,Description [31:17],Reserved,15h0,Reserved [16:13],qinv_cnt_limit,4h1,"Affects QDMA only. If qinv_limit_en is set, this is the limit of qinv from dsc engine through c2h st pfch_evt_fifo that is allowed"[12],qinv_limit_en,4h1,"Affects QDMA only. If set, limit the number of qinvalidation in the pipe from dsc engine through C2H ST pfch_evt_fifo."[11],qinv_arb_stall,1h0,"Affects QDMA only. If set, allow descriptor fetching to continue even if tm_dsc_sts is full."[10],brdg_rro_en,1h0,"If set, enable relaxed ordering for all bridge slave reads to pcie."[9],Reserved,1h0,Reserved [8],pcie_mrs_reg_en,1h0,"If set, pcie max read size used will be defined by register"[7],pcie_mpl_reg_en,1h0,"If set, pcie max payload used will be define by register"[6:0],Reserved,7h0,Reserved |