TxBuff_DLC_Msg_n (CANFD) Register Description
Register Name | TxBuff_DLC_Msg_n |
---|---|
Relative Address | 0x0000000104 |
Absolute Address |
0x00FF060104 (CANFD0) 0x00FF070104 (CANFD1) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | 32 DLC regs for TxBuffer msgs 0 to 31 at 0x0104, 0x014C, etc (0x48 step) |
There are 32 Tx message DLC registers. The first message DLC register is at offset addresss 0x0104. Second DLC register is at 0x014C. The address increment between message sets is 0x048. Note: Data byte are transmitted with CAN or CAN FD frame based on DLC control field. Software Driver name: TB_DLC Original Bit Field Engineering Name: ID
TxBuff_DLC_Msg_n (CANFD) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
DLC | 31:28 | rwNormal read/write | 0 | Data Length Code This is the data length code of the control field of the CAN and CAN FD frame. |
FDF | 27 | rwNormal read/write | 0 | FD Frame Format This bit distinguishes between CAN format and CAN FD format frames. 1 = CAN FD format frame 0 = CAN format frame |
BRS | 26 | rwNormal read/write | 0 | Bit Rate Switch. The BRS bit decides whether the bit rate is switched inside a CAN FD format frame or not (provided BRSD bit is not set in MSR register). 1 = bit rate is switched from the standard bit rate of the Arbitration phase to the preconfigured alternate bit rate of the Data phase inside a CAN FD frame 0 = bit rate is not switched inside a CAN FD frame Note: BRS does not exist in CAN format frames and should be set to 0. |
RSVD2 | 25 | rwNormal read/write | 0 | Reserved field User is expected to write 0. |
EFC | 24 | rwNormal read/write | 0 | Event buffer control: 0 = Don't store TX events 1 = Store TX Events |
MM | 23:16 | rwNormal read/write | 0 | Message Marker Written by software during TX Buffer configuration. Copied into Tx Event buffer for identification of TX message status. |
RSVD1 | 15:0 | rwNormal read/write | 0 | Reserved field User is expected to write 0. |