TxBuff_DLC_Msg_n (CANFD) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

TxBuff_DLC_Msg_n (CANFD) Register Description

Register NameTxBuff_DLC_Msg_n
Relative Address0x0000000104
Absolute Address 0x00FF060104 (CANFD0)
0x00FF070104 (CANFD1)
Width32
TyperwNormal read/write
Reset Value0x00000000
Description32 DLC regs for TxBuffer msgs 0 to 31 at 0x0104, 0x014C, etc (0x48 step)

There are 32 Tx message DLC registers. The first message DLC register is at offset addresss 0x0104. Second DLC register is at 0x014C. The address increment between message sets is 0x048. Note: Data byte are transmitted with CAN or CAN FD frame based on DLC control field. Software Driver name: TB_DLC Original Bit Field Engineering Name: ID

TxBuff_DLC_Msg_n (CANFD) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
DLC31:28rwNormal read/write0Data Length Code
This is the data length code of the control field of the CAN and CAN FD frame.
FDF27rwNormal read/write0FD Frame Format
This bit distinguishes between CAN format and CAN FD format
frames.
1 = CAN FD format frame
0 = CAN format frame
BRS26rwNormal read/write0Bit Rate Switch.
The BRS bit decides whether the bit rate is switched inside a CAN FD format frame or not (provided BRSD bit is not set in MSR register).
1 = bit rate is switched from the standard bit rate of the Arbitration phase to the preconfigured alternate bit rate of the Data phase inside a CAN FD frame
0 = bit rate is not switched inside a CAN FD frame
Note: BRS does not exist in CAN format frames and should be set to 0.
RSVD225rwNormal read/write0Reserved field
User is expected to write 0.
EFC24rwNormal read/write0Event buffer control:
0 = Don't store TX events
1 = Store TX Events
MM23:16rwNormal read/write0Message Marker
Written by software during TX Buffer configuration. Copied into Tx Event buffer for identification of TX message status.
RSVD115:0rwNormal read/write0Reserved field
User is expected to write 0.