TxBuff_Ready_Req (CANFD) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID

AM012

Release Date

2023-08-29

Revision

1.3

TxBuff_Ready_Req (CANFD) Register Description

Register Name	TxBuff_Ready_Req
Relative Address	0x0000000090
Absolute Address	0x00FF060090 (CANFD0) 0x00FF070090 (CANFD1)
Width	32
Type	rwsoRead/write, set only
Reset Value	0x00000000
Description	TxBuffer Ready Request

Notes: 1. Host can set transmission requests for multiple buffers in one write to this register. 2. Write with any value to this register triggers buffer scheduler to redo the scheduling round to find winning buffer (exceptions: when Transfer Layer is in 3-bit Intermission space without locked buffer or if previous scheduling round is already running. In those situation, buffer scheduler trigger is postponed till the event is over). 3. Unnecessary writes to this register might reduce core throughput on the CAN bus. Ensure this register is written only when it is required. Software Driver name: XCANFD_TRR Alternate register name: TX_Buffer_Ready_Request_Register

TxBuff_Ready_Req (CANFD) Register Bit-Field Summary

Field Name	Bits	Type	Reset Value	Description
RR31	31	rwsoRead/write, set only	0x0	TX Buffer_31 Ready Request Description similar as RR0.
RR30	30	rwsoRead/write, set only	0x0	TX Buffer_30 Ready Request Description similar as RR0.
RR29	29	rwsoRead/write, set only	0x0	TX Buffer_29 Ready Request Description similar as RR0.
RR28	28	rwsoRead/write, set only	0x0	TX Buffer_28 Ready Request Description similar as RR0.
RR27	27	rwsoRead/write, set only	0x0	TX Buffer_27 Ready Request Description similar as RR0.
RR26	26	rwsoRead/write, set only	0x0	TX Buffer_26 Ready Request Description similar as RR0.
RR25	25	rwsoRead/write, set only	0x0	TX Buffer_25 Ready Request Description similar as RR0.
RR24	24	rwsoRead/write, set only	0x0	TX Buffer_24 Ready Request Description similar as RR0.
RR23	23	rwsoRead/write, set only	0x0	TX Buffer_23 Ready Request Description similar as RR0.
RR22	22	rwsoRead/write, set only	0x0	TX Buffer_22 Ready Request Description similar as RR0.
RR21	21	rwsoRead/write, set only	0x0	TX Buffer_21 Ready Request Description similar as RR0.
RR20	20	rwsoRead/write, set only	0x0	TX Buffer_20 Ready Request Description similar as RR0.
RR19	19	rwsoRead/write, set only	0x0	TX Buffer_19 Ready Request Description similar as RR0.
RR18	18	rwsoRead/write, set only	0x0	TX Buffer_18 Ready Request Description similar as RR0.
RR17	17	rwsoRead/write, set only	0x0	TX Buffer_17 Ready Request Description similar as RR0.
RR16	16	rwsoRead/write, set only	0x0	TX Buffer_16 Ready Request Description similar as RR0.
RR15	15	rwsoRead/write, set only	0x0	TX Buffer_15 Ready Request Description similar as RR0.
RR14	14	rwsoRead/write, set only	0x0	TX Buffer_14 Ready Request Description similar as RR0.
RR13	13	rwsoRead/write, set only	0x0	TX Buffer_13 Ready Request Description similar as RR0.
RR12	12	rwsoRead/write, set only	0x0	TX Buffer_12 Ready Request Description similar as RR0.
RR11	11	rwsoRead/write, set only	0x0	TX Buffer_11 Ready Request Description similar as RR0.
RR10	10	rwsoRead/write, set only	0x0	TX Buffer_10 Ready Request Description similar as RR0.
RR9	9	rwsoRead/write, set only	0x0	TX Buffer_9 Ready Request Description similar as RR0.
RR8	8	rwsoRead/write, set only	0x0	TX Buffer_8 Ready Request Description similar as RR0.
RR7	7	rwsoRead/write, set only	0x0	TX Buffer_7 Ready Request Description similar as RR0.
RR6	6	rwsoRead/write, set only	0x0	TX Buffer_6 Ready Request Description similar as RR0.
RR5	5	rwsoRead/write, set only	0x0	TX Buffer_5 Ready Request Description similar as RR0.
RR4	4	rwsoRead/write, set only	0x0	TX Buffer_4 Ready Request Description similar as RR0.
RR3	3	rwsoRead/write, set only	0x0	TX Buffer_3 Ready Request Description similar as RR0.
RR2	2	rwsoRead/write, set only	0x0	TX Buffer_2 Ready Request Description similar as RR0.
RR1	1	rwsoRead/write, set only	0x0	TX Buffer_1 Ready Request Description similar as RR0.
RR0	0	rwsoRead/write, set only	0x0	TX Buffer_0 Ready Request This is control bit corresponds to TB0 message in TX RAM. Host writes 1 to indicate buffer is ready for transmission. Core clears this bit when: * Buffer transmission is completed on CAN Bus * If core is in DAR mode, then after one transmission attempt on CAN bus [either successful or unsuccessful (that is, arbitration lost or error)] * If message is cancelled due to cancellation request * Any combination of the above three. Host writes to this bit are ignored when this bit is 1. Note: This register remains in reset when SNOOP mode is enabled.