TxBuff_Ready_Req_Intr_En (CANFD) Register Description
| Register Name | TxBuff_Ready_Req_Intr_En |
|---|---|
| Relative Address | 0x0000000094 |
| Absolute Address |
0x00FF060094 (CANFD0) 0x00FF070094 (CANFD1) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | TX Buffer Ready Request Interrupt Enables |
Software Driver name: XCANFD_IETRS Alternate register name: Interrupt_Enable_TX_Buffer_Ready_Request_Register
TxBuff_Ready_Req_Intr_En (CANFD) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| ERRS31 | 31 | rwNormal read/write | 0x0 | TX Buffer_31 Ready Req Served/Cleared Interrupt Enable Description similar as ERRS0. |
| ERRS30 | 30 | rwNormal read/write | 0x0 | TX Buffer_30 Ready Req Served/Cleared Interrupt Enable Description similar as ERRS0. |
| ERRS29 | 29 | rwNormal read/write | 0x0 | TX Buffer_29 Ready Req Served/Cleared Interrupt Enable Description similar as ERRS0. |
| ERRS28 | 28 | rwNormal read/write | 0x0 | TX Buffer_28 Ready Req Served/Cleared Interrupt Enable Description similar as ERRS0. |
| ERRS27 | 27 | rwNormal read/write | 0x0 | TX Buffer_27 Ready Req Served/Cleared Interrupt Enable Description similar as ERRS0. |
| ERRS26 | 26 | rwNormal read/write | 0x0 | TX Buffer_26 Ready Req Served/Cleared Interrupt Enable Description similar as ERRS0. |
| ERRS25 | 25 | rwNormal read/write | 0x0 | TX Buffer_25 Ready Req Served/Cleared Interrupt Enable Description similar as ERRS0. |
| ERRS24 | 24 | rwNormal read/write | 0x0 | TX Buffer_24 Ready Req Served/Cleared Interrupt Enable Description similar as ERRS0. |
| ERRS23 | 23 | rwNormal read/write | 0x0 | TX Buffer_23 Ready Req Served/Cleared Interrupt Enable Description similar as ERRS0. |
| ERRS22 | 22 | rwNormal read/write | 0x0 | TX Buffer_22 Ready Req Served/Cleared Interrupt Enable Description similar as ERRS0. |
| ERRS21 | 21 | rwNormal read/write | 0x0 | TX Buffer_21 Ready Req Served/Cleared Interrupt Enable Description similar as ERRS0. |
| ERRS20 | 20 | rwNormal read/write | 0x0 | TX Buffer_20 Ready Req Served/Cleared Interrupt Enable Description similar as ERRS0. |
| ERRS19 | 19 | rwNormal read/write | 0x0 | TX Buffer_19 Ready Req Served/Cleared Interrupt Enable Description similar as ERRS0. |
| ERRS18 | 18 | rwNormal read/write | 0x0 | TX Buffer_18 Ready Req Served/Cleared Interrupt Enable Description similar as ERRS0. |
| ERRS17 | 17 | rwNormal read/write | 0x0 | TX Buffer_17 Ready Req Served/Cleared Interrupt Enable Description similar as ERRS0. |
| ERRS16 | 16 | rwNormal read/write | 0x0 | TX Buffer_16 Ready Req Served/Cleared Interrupt Enable Description similar as ERRS0. |
| ERRS15 | 15 | rwNormal read/write | 0x0 | TX Buffer_15 Ready Req Served/Cleared Interrupt Enable Description similar as ERRS0. |
| ERRS14 | 14 | rwNormal read/write | 0x0 | TX Buffer_14 Ready Req Served/Cleared Interrupt Enable Description similar as ERRS0. |
| ERRS13 | 13 | rwNormal read/write | 0x0 | TX Buffer_13 Ready Req Served/Cleared Interrupt Enable Description similar as ERRS0. |
| ERRS12 | 12 | rwNormal read/write | 0x0 | TX Buffer_12 Ready Req Served/Cleared Interrupt Enable Description similar as ERRS0. |
| ERRS11 | 11 | rwNormal read/write | 0x0 | TX Buffer_11 Ready Req Served/Cleared Interrupt Enable Description similar as ERRS0. |
| ERRS10 | 10 | rwNormal read/write | 0x0 | TX Buffer_10 Ready Req Served/Cleared Interrupt Enable Description similar as ERRS0. |
| ERRS9 | 9 | rwNormal read/write | 0x0 | TX Buffer_9 Ready Req Served/Cleared Interrupt Enable Description similar as ERRS0. |
| ERRS8 | 8 | rwNormal read/write | 0x0 | TX Buffer_8 Ready Req Served/Cleared Interrupt Enable Description similar as ERRS0. |
| ERRS7 | 7 | rwNormal read/write | 0x0 | TX Buffer_7 Ready Req Served/Cleared Interrupt Enable Description similar as ERRS0. |
| ERRS6 | 6 | rwNormal read/write | 0x0 | TX Buffer_6 Ready Req Served/Cleared Interrupt Enable Description similar as ERRS0. |
| ERRS5 | 5 | rwNormal read/write | 0x0 | TX Buffer_5 Ready Req Served/Cleared Interrupt Enable Description similar as ERRS0. |
| ERRS4 | 4 | rwNormal read/write | 0x0 | TX Buffer_4 Ready Req Served/Cleared Interrupt Enable Description similar as ERRS0. |
| ERRS3 | 3 | rwNormal read/write | 0x0 | TX Buffer_3 Ready Req Served/Cleared Interrupt Enable Description similar as ERRS0. |
| ERRS2 | 2 | rwNormal read/write | 0x0 | TX Buffer_2 Ready Req Served/Cleared Interrupt Enable Description similar as ERRS0. |
| ERRS1 | 1 | rwNormal read/write | 0x0 | TX Buffer_1 Ready Req Served/Cleared Interrupt Enable Description similar as ERRS0. |
| ERRS0 | 0 | rwNormal read/write | 0x0 | TX Buffer_0 Ready Req Served/Cleared Interrupt Enable 1 = enables setting TXRRS bit in ISR when RR0 bit in TRR register clears 0 = TXRRS bit in ISR does not set if RR0 bit in TRR register clears |