TxEvent_DLC_Reg_n (CANFD) Register Description
Register Name | TxEvent_DLC_Reg_n |
---|---|
Relative Address | 0x0000002004 |
Absolute Address |
0x00FF062004 (CANFD0) 0x00FF072004 (CANFD1) |
Width | 32 |
Type | roRead-only |
Reset Value | 0x00000000 |
Description | 32 DLC regs for TxEvent msgs 0 to 31 at 0x2004, 0x200C, etc (0x08 step) |
There can be up to 32 Tx Events stored in the Tx FIFO. The first Tx event DLC register is at offset 0x2000. Second register is at 0x2008. The address increment between registers is 0x008. Software Driver name: TEF_DLC Original Bit Field Engineering Name: ID
TxEvent_DLC_Reg_n (CANFD) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
DLC | 31:28 | roRead-only | 0 | Data Length Code This is the data length code of the control field of the CAN and CAN FD frame. |
FDF | 27 | roRead-only | 0 | FD Frame Format This bit distinguishes between CAN format and CAN FD format frames. 1 = CAN FD format frame 0 = CAN format frame |
BRS | 26 | roRead-only | 0 | Bit Rate Switch. The BRS bit decides whether the bit rate is switched inside a CAN FD format frame or not (provided BRSD bit is not set in MSR register). 1 = bit rate is switched from the standard bit rate of the Arbitration phase to the preconfigured alternate bit rate of the Data phase inside a CAN FD frame 0 = bit rate is not switched inside a CAN FD frame Note: BRS does not exist in CAN format frames and should be set to 0. |
ET | 25:24 | roRead-only | 0 | Event Type 11 -> Transmitted. 01 -> Transmitted in spite of cancellation request or DAR mode Transmissions. Same bit coding is uded for DAR mode transmissions. 00 -> Reserved. 10 -> Reserved. |
MM | 23:16 | roRead-only | 0 | Message Marker. Written by software during TX Buffer configuration. Copied into Tx Event buffer for identification of TX message status. |
TS | 15:0 | roRead-only | 0 | Timestamp captured after SOF bit. This is written by core for status purpose for successfully trasmitted message. Software Driver name: TS |