TxEvent_FIFO_Status (CANFD) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

TxEvent_FIFO_Status (CANFD) Register Description

Register NameTxEvent_FIFO_Status
Relative Address0x00000000A0
Absolute Address 0x00FF0600A0 (CANFD0)
0x00FF0700A0 (CANFD1)
Width14
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionTx Event Buffer Status

Alternate register name: TX_Event_FIFO_Status_Register

TxEvent_FIFO_Status (CANFD) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
FL13:8roRead-only0x0Fill Level (0-32). Number of stored message in TX Event FIFO starting from [TXE_RI] bit in this register.
For example, if [RXE_FL] = 5 and [TXE_RI] = 3 then the TX Event FIFO has five messages starting from Read Index 3 (Start address 0x2018).
Note: [TXE_FL] is maintained if SW_Reset [CEN] bit is cleared.
Note: [TXE_FL] gets reset to 0 if soft or hard reset is asserted.
Software Driver name: FL
IRI 7woWrite-only0x0Increment Read Index by 1. With each software write setting this bit as 1, the controller increments Read index [RI] by 1 and updates the fill level; decrements by 1.
If FILL level is 0, setting this bit has no effect.
Note: The FILL level might remain unchanged when [IRI] is written if the controller is just finishing a successful transmission and incrementing internal write index.
Note: This bit always read as 0.
Software Driver name: IRI
RI 4:0roRead-only0x0Read Index. Range is 0 to 31d.
Each time [IRI] bit is set = 1, the controller increments [RI] by 1 (provided FILL level is not 0) and maintains it for software to access next available Message. Next Message start location is defined by [RI]:
0: start location is 0x2000
1: start location is 0x2008
etc
1F: start location is 0x20F8
Note: [RI] value is maintained when [CEN] bit is cleared = 0.
Note: [RI] gets reset to 0 if a software or POR reset is asserted.
Software Driver name: RI