aximm_bridge_Port (CPM4_DMA_ATTR) Register

Versal Adaptive SoC Register Reference (AM012)
Document ID
AM012
Release Date
2023-08-29
Revision
1.3

aximm_bridge_Port (CPM4_DMA_ATTR) Register Description

Register Nameaximm_bridge_Port
Relative Address0x00000000D0
Absolute Address 0x00FCA700D0 (CPM4_DMA_ATTR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionSteering mode to determine which MM Master Port Bridge transactions will use.
0:
bridge requests will be issued on MM0
1:
bridge requests will be issued on MM1

This register should only be written to during reset of the PCIe block Alternate register name: attr_dma_aximm_bridge_port

aximm_bridge_Port (CPM4_DMA_ATTR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr 0rwNormal read/write0x0Steering mode to determine which MM Master Port Bridge transactions will use.
0:
bridge requests will be issued on MM0
1:
bridge requests will be issued on MM1