ccix_per_pkt_hdr_3 (CPM4_DVSEC1) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

ccix_per_pkt_hdr_3 (CPM4_DVSEC1) Register Description

Register Nameccix_per_pkt_hdr_3
Relative Address0x0000000DD8
Absolute Address 0x00FCFC0DD8 (CPM4_DVSEC1)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionCCIX PER Message Capability (Physical Function #0 only)

ccix_per_pkt_hdr_3 (CPM4_DVSEC1) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
byte1231:24rwNormal read/write0x0Packet Header Byte 12
byte1323:16rwNormal read/write0x0Packet Header Byte 13
byte1415:8rwNormal read/write0x0Packet Header Byte 14
byte15 7:0rwNormal read/write0x0Packet Header Byte 15