por_cxg_ha_aux_ctl_u_cxrh_nid72 (CPM4_CMN600) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

por_cxg_ha_aux_ctl_u_cxrh_nid72 (CPM4_CMN600) Register Description

Register Namepor_cxg_ha_aux_ctl_u_cxrh_nid72
Relative Address0x0000910A08
Absolute Address 0x00FC910A08 (CPM4_CMN)
Width64
TypemixedMixed types. See bit-field details.
Reset Value0x00000008
DescriptionFunctions as the auxiliary control register for CXHA.

por_cxg_ha_aux_ctl_u_cxrh_nid72 (CPM4_CMN600) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved63:6razRead as zero0x0reserved
disable_cg_flopen 5rwNormal read/write0x0Disables enhanced flop enable control for dynamic power savings
disable_secure_access 4rwNormal read/write0x0Converts all accesses to non-secure
early_compack_en 3rwNormal read/write0x1Early CompAck enable; enables sending early CompAck on CCIX for requests that require CompAck
remote_chia_rnf_present 2rwNormal read/write0x0Indicates existence of CHIA RN-F in system; HA uses this indication to send SnpToS or SnpToSC 1b0: HA converts SnpShared, SnpClean, and SnpNotSharedDirty to SnpToSC 1b1: HA converts SnpShared, SnpClean, and SnpNotSharedDirty to SnpToS
snoop_dataret_disable 1rwNormal read/write0x0Disables setting data return for CCIX snoop requests for all CHI snoop opcodes
cg_disable 0rwNormal read/write0x0Disables clock gating when set