por_cxg_ha_errctlr_NS_u_cxrh_nid68 (CPM4_CMN600) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

por_cxg_ha_errctlr_NS_u_cxrh_nid68 (CPM4_CMN600) Register Description

Register Namepor_cxg_ha_errctlr_NS_u_cxrh_nid68
Relative Address0x0000817108
Absolute Address 0x00FC817108 (CPM4_CMN)
Width64
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionFunctions as the non-secure error control register. Controls whether specific error-handling interrupts and error detection/deferment are enabled.

por_cxg_ha_errctlr_NS_u_cxrh_nid68 (CPM4_CMN600) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved63:9razRead as zero0x0reserved
CFI 8rwNormal read/write0x0Enables corrected error interrupt as specified in por_cxg_ha_errfr.CFI
Reserved 7:4razRead as zero0x0reserved
FI 3rwNormal read/write0x0Enables fault handling interrupt for all detected deferred errors as specified in por_cxg_ha_errfr.FI
UI 2rwNormal read/write0x0Enables uncorrected error interrupt as specified in por_cxg_ha_errfr.UI
DE 1rwNormal read/write0x0Enables error deferment as specified in por_cxg_ha_errfr.DE
ED 0rwNormal read/write0x0Enables error detection as specified in por_cxg_ha_errfr.ED