por_cxg_ha_pmu_event_sel_u_cxrh_nid68 (CPM4_CMN600) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

por_cxg_ha_pmu_event_sel_u_cxrh_nid68 (CPM4_CMN600) Register Description

Register Namepor_cxg_ha_pmu_event_sel_u_cxrh_nid68
Relative Address0x0000816000
Absolute Address 0x00FC816000 (CPM4_CMN)
Width64
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionSpecifies the PMU event to be counted as a 6-bit ID with the following encodings: 6b000000: CXHA_PMU_EVENT_NULL 6b100001: CXHA_PMU_EVENT_RDDATBYP 6b100010: CXHA_PMU_EVENT_CHIRSP_UP_STALL 6b100011: CXHA_PMU_EVENT_CHIDAT_UP_STALL 6b100100: CXHA_PMU_EVENT_SNPPCRD_LNK0_STALL 6b100101: CXHA_PMU_EVENT_SNPPCRD_LNK1_STALL 6b100110: CXHA_PMU_EVENT_SNPPCRD_LNK2_STALL 6b100111: CXHA_PMU_EVENT_REQTRK_OCC 6b101000: CXHA_PMU_EVENT_RDB_OCC 6b101001: CXHA_PMU_EVENT_RDBBYP_OCC 6b101010: CXHA_PMU_EVENT_WDB_OCC 6b101011: CXHA_PMU_EVENT_SNPTRK_OCC 6b101100: CXHA_PMU_EVENT_SDB_OCC 6b101101: CXHA_PMU_EVENT_SNPHAZ_OCC

por_cxg_ha_pmu_event_sel_u_cxrh_nid68 (CPM4_CMN600) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved63:36razRead as zero0x0reserved
pmu_occup1_id35:32rwNormal read/write0x0CXHA PMU occupancy event selector ID
Reserved31:30razRead as zero0x0reserved
pmu_event3_id29:24rwNormal read/write0x0CXHA PMU Event 3 ID
Reserved23:22razRead as zero0x0reserved
pmu_event2_id21:16rwNormal read/write0x0CXHA PMU Event 2 ID
Reserved15:14razRead as zero0x0reserved
pmu_event1_id13:8rwNormal read/write0x0CXHA PMU Event 1 ID
Reserved 7:6razRead as zero0x0reserved
pmu_event0_id 5:0rwNormal read/write0x0CXHA PMU Event 0 ID