por_cxla_ccix_prop_capabilities_u_cxrh_nid68 (CPM4_CMN600) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID: AM012
Release Date: 2023-08-29
Revision: 1.3

por_cxla_ccix_prop_capabilities_u_cxrh_nid68 (CPM4_CMN600) Register Description

Register Name	por_cxla_ccix_prop_capabilities_u_cxrh_nid68
Relative Address	0x0000824C00
Absolute Address	0x00FC824C00 (CPM4_CMN)
Width	64
Type	mixedMixed types. See bit-field details.
Reset Value	0x00000100
Description	Contains CCIX-supported properties.

por_cxla_ccix_prop_capabilities_u_cxrh_nid68 (CPM4_CMN600) Register Bit-Field Summary

Field Name	Bits	Type	Reset Value	Description
Reserved	63:11	razRead as zero	0x0	reserved
nomessagepack	10	roRead-only	0x0	No message packing only supported 1b0: False 1b1: True
maxpacketsize	9:7	roRead-only	0x2	Maximum packet size supported 3b000: 128B 3b001: 256B 3b010: 512B
pktheader	6	roRead-only	0x0	Packet header supported 1b0: PCIe compatible header 1b1: Optimized header
addrwidth	5:3	roRead-only	0x0	Address width supported 3b000: 48b 3b001: 52b 3b010: 56b 3b011: 60b 3b100: 64b
cachelinesize	2	roRead-only	0x0	Cacheline size supported 1b0: 64B 1b1: 128B
partialcachestates	1	roRead-only	0x0	Partial cache states supported 1b0: False 1b1: True
nocompack	0	roRead-only	0x0	No CompAck supported 1b0: False 1b1: True