por_cxla_ccix_prop_configured_u_cxrh_nid72 (CPM4_CMN600) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

por_cxla_ccix_prop_configured_u_cxrh_nid72 (CPM4_CMN600) Register Description

Register Namepor_cxla_ccix_prop_configured_u_cxrh_nid72
Relative Address0x0000920C08
Absolute Address 0x00FC920C08 (CPM4_CMN)
Width64
TypemixedMixed types. See bit-field details.
Reset Value0x00000400
DescriptionContains CCIX-configured properties.

por_cxla_ccix_prop_configured_u_cxrh_nid72 (CPM4_CMN600) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved63:11razRead as zero0x0reserved
nomessagepack10rwNormal read/write0x1No message packing configured 1b0: False 1b1: True
maxpacketsize 9:7rwNormal read/write0x0Maximum packet size configured 3b000: 128B 3b001: 256B 3b010: 512B
pktheader 6rwNormal read/write0x0Packet header configured 1b0: PCIe compatible header 1b1: Optimized header
addrwidth 5:3rwNormal read/write0x0Address width configured 3b000: 48b 3b001: 52b 3b010: 56b 3b011: 60b 3b100: 64b
cachelinesize 2rwNormal read/write0x0CacheLine size configured 1b0: 64B 1b1: 128B
partialcachestates 1rwNormal read/write0x0Partial cache states configured 1b0: False 1b1: True
nocompack 0rwNormal read/write0x0No CompAck configured 1b0: False 1b1: True