por_cxla_linkid_to_pcie_bus_num_u_cxrh_nid68 (CPM4_CMN600) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID: AM012
Release Date: 2023-08-29
Revision: 1.3

por_cxla_linkid_to_pcie_bus_num_u_cxrh_nid68 (CPM4_CMN600) Register Description

Register Name	por_cxla_linkid_to_pcie_bus_num_u_cxrh_nid68
Relative Address	0x0000824C78
Absolute Address	0x00FC824C78 (CPM4_CMN)
Width	64
Type	mixedMixed types. See bit-field details.
Reset Value	0x00000000
Description	Specifies the mapping of CCIX Link ID to PCIe bus number.

por_cxla_linkid_to_pcie_bus_num_u_cxrh_nid68 (CPM4_CMN600) Register Bit-Field Summary

Field Name	Bits	Type	Reset Value	Description
Reserved	63:48	razRead as zero	0x0	reserved
link2_pcie_dev_num	47:43	rwNormal read/write	0x0	PCIe Device number for Link ID 2
link2_pcie_func_num	42:40	rwNormal read/write	0x0	PCIe Function number for Link ID 2
link2_pcie_bus_num	39:32	rwNormal read/write	0x0	PCIe bus number for Link ID 2
link1_pcie_dev_num	31:27	rwNormal read/write	0x0	PCIe Device number for Link ID 1
link1_pcie_func_num	26:24	rwNormal read/write	0x0	PCIe Function number for Link ID 1
link1_pcie_bus_num	23:16	rwNormal read/write	0x0	PCIe bus number for Link ID 1
link0_pcie_dev_num	15:11	rwNormal read/write	0x0	PCIe Device number for Link ID 0
link0_pcie_func_num	10:8	rwNormal read/write	0x0	PCIe Function number for Link ID 0
link0_pcie_bus_num	7:0	rwNormal read/write	0x0	PCIe bus number for Link ID 0