por_cxla_pmu_event_sel_u_cxrh_nid72 (CPM4_CMN600) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

por_cxla_pmu_event_sel_u_cxrh_nid72 (CPM4_CMN600) Register Description

Register Namepor_cxla_pmu_event_sel_u_cxrh_nid72
Relative Address0x0000922000
Absolute Address 0x00FC922000 (CPM4_CMN)
Width64
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionSpecifies the PMU event to be counted.

por_cxla_pmu_event_sel_u_cxrh_nid72 (CPM4_CMN600) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved63:29razRead as zero0x0reserved
pmu_event3_id28:24rwNormal read/write0x0CXLA PMU Event 3 ID; see pmu_event0_id for encodings
Reserved23:21razRead as zero0x0reserved
pmu_event2_id20:16rwNormal read/write0x0CXLA PMU Event 2 ID; see pmu_event0_id for encodings
Reserved15:13razRead as zero0x0reserved
pmu_event1_id12:8rwNormal read/write0x0CXLA PMU Event 1 ID; see pmu_event0_id for encodings
Reserved 7:5razRead as zero0x0reserved
pmu_event0_id 4:0rwNormal read/write0x0CXLA PMU Event 0 ID 5h00: No event 5h01: RX TLP for Link 0 5h02: RX TLP for Link 1 5h03: RX TLP for Link 2 5h04: TX TLP for Link 0 5h05: TX TLP for Link 1 5h06: TX TLP for Link 2 5h07: RX CXS for Link 0 5h08: RX CXS for Link 1 5h09: RX CXS for Link 2 5h0A: TX CXS for Link 0 5h0B: TX CXS for Link 1 5h0B: TX CXS for Link 2 5h0D: Average RX TLP size in DWs 5h0E: Average TX TLP size in DWs 5h0F: Average RX TLP size in CCIX messages 5h10: Average TX TLP size in CCIX messages 5h11: Average size of RX CXS in DWs within a beat 5h12: Average size of TX CXS in DWs within a beat 5h13: TX CXS link credit backpressure 5h14: RX TLP buffer full and backpressured 5h15: TX TLP buffer full and backpressured 5h16: Average latency to process an RX TLP 5h17: Average latency to form a TX TLP