por_cxla_tx_cxs_attr_capabilities_u_cxrh_nid72 (CPM4_CMN600) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

por_cxla_tx_cxs_attr_capabilities_u_cxrh_nid72 (CPM4_CMN600) Register Description

Register Namepor_cxla_tx_cxs_attr_capabilities_u_cxrh_nid72
Relative Address0x0000920C10
Absolute Address 0x00FC920C10 (CPM4_CMN)
Width64
TypemixedMixed types. See bit-field details.
Reset Value0x00000030
DescriptionContains TX CXS supported attributes.

por_cxla_tx_cxs_attr_capabilities_u_cxrh_nid72 (CPM4_CMN600) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved63:10razRead as zero0x0reserved
txcxscontrolreplication 9:8roRead-only0x0TX CXS control replication supported 2b00: None 2b01: Duplicate 2b10: Triplicate
txcxsdatacheck 7:6roRead-only0x0TX CXS datacheck supported 2b00: None 2b01: Parity 2b10: SECDED
txcxserrorfullpkt 5roRead-only0x1TX CXS error full packet supported 1b0: False 1b1: True
txcxscontinuousdata 4roRead-only0x1TX CXS continuous data supported 1b0: False 1b1: True
txcxsmaxpktperflit 3:2roRead-only0x0TX CXS maximum packets per flit supported 2b00: 2 2b01: 3 2b10: 4
txcxsdataflitwidth 1:0roRead-only0x0TX CXS data flit width supported 2b00: 256b 2b01: 512b 2b10: 1024b