por_dt_dtc_ctl_u_hnd_nid8 (CPM4_CMN600) Register

Versal Adaptive SoC Register Reference (AM012)
Document ID
AM012
Release Date
2023-08-29
Revision
1.3

por_dt_dtc_ctl_u_hnd_nid8 (CPM4_CMN600) Register Description

Register Namepor_dt_dtc_ctl_u_hnd_nid8
Relative Address0x0000130A00
Absolute Address 0x00FC130A00 (CPM4_CMN)
Width64
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionFunctions as the debug trace control register.

por_dt_dtc_ctl_u_hnd_nid8 (CPM4_CMN600) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved63:11razRead as zero0x0reserved
cg_disable10rwNormal read/write0x0Disables DT architectural clock gates
cross_trigger_count 9:4rwNormal read/write0x0Number of cross triggers received before trace enable NOTE: Only applicable if dt_wait_for_trigger is set to 1.
dt_wait_for_trigger 3rwNormal read/write0x0Enables waiting for cross trigger before trace enable
atbtrigger_en 2rwNormal read/write0x0ATB trigger enable
dbgtrigger_en 1rwNormal read/write0x0DBGWATCHTRIG enable
dt_en 0rwNormal read/write0x0Enables debug, trace, and PMU features