por_dt_pmcr_u_hnd_nid8 (CPM4_CMN600) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

por_dt_pmcr_u_hnd_nid8 (CPM4_CMN600) Register Description

Register Namepor_dt_pmcr_u_hnd_nid8
Relative Address0x0000132100
Absolute Address 0x00FC132100 (CPM4_CMN)
Width64
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionFunctions as the PMU control register.

por_dt_pmcr_u_hnd_nid8 (CPM4_CMN600) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved63:7razRead as zero0x0reserved
ovfl_intr_en 6rwNormal read/write0x0Enables INTREQPMU assertion on PMU counter overflow
cntr_rst 5rwNormal read/write0x0Enables clearing of live counters upon assertion of por_dt_pmsrr.ss_req or PMUSNAPSHOTREQ
cntcfg 4:1rwNormal read/write0x0Groups adjacent 32-bit registers into a 64-bit register
pmu_en 0rwNormal read/write0x0Enables PMU features