por_dt_pmcr_u_hnd_nid8 (CPM4_CMN600) Register Description
Register Name | por_dt_pmcr_u_hnd_nid8 |
---|---|
Relative Address | 0x0000132100 |
Absolute Address | 0x00FC132100 (CPM4_CMN) |
Width | 64 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | Functions as the PMU control register. |
por_dt_pmcr_u_hnd_nid8 (CPM4_CMN600) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 63:7 | razRead as zero | 0x0 | reserved |
ovfl_intr_en | 6 | rwNormal read/write | 0x0 | Enables INTREQPMU assertion on PMU counter overflow |
cntr_rst | 5 | rwNormal read/write | 0x0 | Enables clearing of live counters upon assertion of por_dt_pmsrr.ss_req or PMUSNAPSHOTREQ |
cntcfg | 4:1 | rwNormal read/write | 0x0 | Groups adjacent 32-bit registers into a 64-bit register |
pmu_en | 0 | rwNormal read/write | 0x0 | Enables PMU features |