por_dt_trace_control_u_hnd_nid8 (CPM4_CMN600) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

por_dt_trace_control_u_hnd_nid8 (CPM4_CMN600) Register Description

Register Namepor_dt_trace_control_u_hnd_nid8
Relative Address0x0000130A30
Absolute Address 0x00FC130A30 (CPM4_CMN)
Width64
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionFunctions as the trace control register.

por_dt_trace_control_u_hnd_nid8 (CPM4_CMN600) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved63:9razRead as zero0x0reserved
cc_enable 8rwNormal read/write0x0Cycle count enable
timestamp_period 7:5rwNormal read/write0x0Time stamp packet insertion period 3b000: Time stamp disabled 3b011: Time stamp every 8K clock cycles 3b100: Time stamp every 16K clock cycles 3b101: Time stamp every 32K clock cycles 3b110: Time stamp every 64K clock cycles
async_period 4:0rwNormal read/write0x0Alignment sync packet insertion period 5h00: Alignment sync disabled 5h08: Alignment sync inserted after 256B of trace 5h09: Alignment sync inserted after 512B of trace 5h14: Alignment sync inserted after 1048576B of trace NOTE: All other values are reserved.