por_dtm_control_u_smxp_2_0 (CPM4_CMN600) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

por_dtm_control_u_smxp_2_0 (CPM4_CMN600) Register Description

Register Namepor_dtm_control_u_smxp_2_0
Relative Address0x000080A100
Absolute Address 0x00FC80A100 (CPM4_CMN)
Width64
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionFunctions as the DTM control register.

por_dtm_control_u_smxp_2_0 (CPM4_CMN600) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved63:4razRead as zero0x0reserved
trace_no_atb 3rwNormal read/write0x0When set, trace packet is not delivered out of ATB, and FIFO entry holds the first trace packet
sample_profile_enable 2rwNormal read/write0x0Enables sample profile function
trace_tag_enable 1rwNormal read/write0x0Watchpoint trace tag enable 1b1: Trace tag enabled 1b0: No trace tag
dtm_enable 0rwNormal read/write0x0Enables debug watchpoint and PMU function; prior to writing this bit, all other DT configuration registers must be programmed; once this bit is set, other DT configuration registers must not be modified